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參數(shù)資料
| 型號(hào)： | CY62148VLL-70BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 MoBL Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 70 ns, PBGA36 |
| 封裝： | 7 X 8.50 X 1.50 MM, FINE PITCH, TBGA-36 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 272K |
| 代理商： | CY62148VLL-70BAI |
CY62148CV25/30/33
MoBL
Document #: 38-05035 Rev. *A
Page 5 of 13
AC Test Loads and Waveforms
R1
Parameters
R1
R2
R
TH
V
TH
2.5V
16.6
15.4
8.0
1.20
3.0V
1.105
1.550
0.645
1.75
3.3V
1.216
1.374
0.645
1.75
Unit
K Ohms
K Ohms
K Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
Description
Conditions
Min.
1.5
Typ.
[4]
Max.
V
ccmax
Unit
V
V
CC
for Data Retention
I
CCDR
Data Retention Current
V
CC
= 1.5V
CE > V
CC
0.2V,
V
IN
> V
CC
0.2V or V
IN
< 0.2V
3
10
μ
A
t
CDR[5]
Chip Deselect to Data
Retention Time
Operation Recovery
Time
0
ns
t
R[6]
t
RC
ns
Data Retention Waveform
Note:
6.
Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
μ
s or stable at V
CC(min.)
>
50
μ
s.
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH
é
VENIN EQUIVALENT
R
TH
ALL INPUT PULSES
Fall time: 1 V/ns
Rise Time: 1 V/ns
V
CC(min.)
t
R
V
CC(min.)
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
CE
V
CC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62148VLL-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 512K x 8 70ns 36-Pin FBGA T/R |
| CY62148VLL-70SI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 512K x 8 70ns 32-Pin SOIC |
| CY62148VLL-70ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4M (512K x 8) Static RAM |
| CY62148VLL-70ZXIT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62148VN | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4 Mbit (512K x 8) Static RAM |
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