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參數(shù)資料
| 型號： | CY62148V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quadruple 2-Input Positive-OR Gate 14-TSSOP -40 to 85 |
| 中文描述： | 為512k × 8的MoBL靜態(tài)RAM |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 272K |
| 代理商： | CY62148V |
512K x 8 MoBL Static RAM
CY62148CV25/30/33
MoBL
Cypress Semiconductor Corporation
Document #: 38-05035 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised September 7, 2001
408-943-2600
Features
High Speed
—
55 ns and 70 ns availability
Low voltage range:
—
CY62148CV25: 2.2V
–
2.7V
—
CY62148CV30: 2.7V
–
3.3V
—
CY62148CV33: 3.0V
–
3.6V
Pin compatible with CY62148V
Ultra low active power
—
Typical active current: 1.5 mA @ f = 1MHz
—
Typical active current: 5.5 mA @ f = f
max
(70 ns speed)
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62148CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in por-
table applications such as cellular telephones. The device also
has an automatic power-down feature that significantly reduc-
es power consumption by 80% when addresses are not tog-
gling. The device can be put into standby mode when dese-
lected (CE HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location speci-
fied on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
The CY62148CV25/30/33 are available in a 36-ball FBGA
package.
Logic Block Diagram
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
R
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
CE
A
1
A
1
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62148VLL-70ZI | Quadruple 2-Input Positive-OR Gate 14-TSSOP -40 to 85 |
| CY62148DV30L | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55BVI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55BVXI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55SXI | 4-Mb (512K x 8) MoBL Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62148V_02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4M (512K x 8) Static RAM |
| CY62148VLL70BAI | 制造商:cypress 功能描述:* |
| CY62148VLL-70BAI | 制造商:Rochester Electronics LLC 功能描述:4MB (512K X 8)- SLOW ASYNCH SRAM - Bulk |
| CY62148VLL-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 512K x 8 70ns 36-Pin FBGA T/R |
| CY62148VLL-70SI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 512K x 8 70ns 32-Pin SOIC |
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