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參數(shù)資料
| 型號： | CY62148V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quadruple 2-Input Positive-OR Gate 14-TSSOP -40 to 85 |
| 中文描述： | 為512k × 8的MoBL靜態(tài)RAM |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 272K |
| 代理商： | CY62148V |
CY62148CV25/30/33
MoBL
Document #: 38-05035 Rev. *A
Page 6 of 13
Switching Characteristics
Over the Operating Range
[7]
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
7.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
/I
and 30 pF load capacitance.
8.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
9.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11.
The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[8]
OE HIGH to High Z
[9]
CE LOW to Low Z
[8]
CE HIGH to High Z
[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
10
10
20
25
0
0
55
70
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[8, 9]
WE HIGH to Low Z
[8]
55
45
45
0
0
45
30
0
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
5
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62148VLL-70ZI | Quadruple 2-Input Positive-OR Gate 14-TSSOP -40 to 85 |
| CY62148DV30L | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55BVI | 4-Mb (512K x 8) MoBL Static RAM |
| CY62148DV30L-55BVXI | 4-Mb (512K x 8) MoBL Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62148V_02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4M (512K x 8) Static RAM |
| CY62148VLL70BAI | 制造商:cypress 功能描述:* |
| CY62148VLL-70BAI | 制造商:Rochester Electronics LLC 功能描述:4MB (512K X 8)- SLOW ASYNCH SRAM - Bulk |
| CY62148VLL-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 512K x 8 70ns 36-Pin FBGA T/R |
| CY62148VLL-70SI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 4M-Bit 512K x 8 70ns 32-Pin SOIC |
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