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參數(shù)資料
| 型號： | CY62148L-55SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | 0.450 INCH, PLASTIC, SOIC-32 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 200K |
| 代理商： | CY62148L-55SC |
CY62148
3
PRELIMINARY
AC Test Loads and Waveforms
Switching Characteristics
[3,6]
Over the Operating Range
62148–55
62148–70
Parameter
READ CYCLE
Description
Min.
Max.
Min.
Max.
Unit
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[9]
Read Cycle Time
55
70
ns
Address to Data Valid
55
70
ns
Data Hold from Address Change
3
3
ns
CE LOW to Data Valid
55
70
ns
OE LOW to Data Valid
20
35
ns
OE LOW to Low Z
OE HIGH to High Z
[7, 8]
CE LOW to Low Z
[8]
CE HIGH to High Z
[7, 8]
0
0
ns
20
25
ns
3
3
ns
20
25
ns
CE LOW to Power-Up
0
0
ns
CE HIGH to Power-Down
55
70
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Shaded areas contain advance information.
Notes
6.
Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100pF load capacitance.
7.
t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
9.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Write Cycle Time
55
70
ns
CE LOW to Write End
45
60
ns
Address Set-Up to Write End
45
60
ns
Address Hold from Write End
0
0
ns
Address Set-Up to Write Start
0
0
ns
WE Pulse Width
45
50
ns
Data Set-Up to Write End
45
55
ns
Data Hold from Write End
WE HIGH to Low Z
[8]
WE LOW to High Z
[7,8]
0
0
ns
3
3
ns
20
25
ns
109–3
109–4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
≤
3ns
≤
3 ns
OUTPUT
R1 481
R1 480
R2
255
R2
255
167
Equivalent to:
VENIN EQUIVALENT
THé
1.73V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62148BLL-70ZRI | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT02; Number of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle |
| CY62148B | 512K x 8 Static RAM |
| CY62148BLL-70SC | 512K x 8 Static RAM |
| CY62148BLL-70SI | 512K x 8 Static RAM |
| CY62148BLL-70ZC | 512K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| cy62148l70sc | 制造商:Cypress Semiconductor 功能描述: |
| CY62148L-70SC | 制造商:Cypress Semiconductor 功能描述:SRAM CMOS 4M SMD 62148 SOIC32 |
| CY62148L-70SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62148L-70ZSC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62148L-70ZSI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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