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參數(shù)資料
| 型號： | CY62148BNSL-70SXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (512K x 8) Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| 封裝： | 0.450 INCH, LEAD FREE, SOIC-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 462K |
| 代理商： | CY62148BNSL-70SXI |
4-Mbit (512K x 8) Static RAM
CY62148BN MoBL
Cypress Semiconductor Corporation
Document #: 001-06517 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised March 1, 2007
Features
4.5V–5.5V operation
Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current:12.5 mA @ f = fmax
Low standby current
Automatic power down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
CMOS for optimum speed and power
Available in standard Pb-free and non Pb-free 32-lead
(450-mil) SOIC and 32-lead TSOP II packages
Functional Description
The CY62148BN is a high performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and tri-state drivers. This device
has an automatic power down feature that reduces power
consumption by more than 99% when deselected.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH for
read. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) go into a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE LOW and WE LOW).
1
A
1
A
Logic Block Diagram
A
1
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512
ARRAY
x
K
8
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
2
A
1
A
3
CE
A
8
A
9
A
1
A
1
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