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參數(shù)資料
| 型號(hào)： | CY62148BLL-70SI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| 封裝： | 0.450 INCH, PLASTIC, SOIC-32 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大小： | 189K |
| 代理商： | CY62148BLL-70SI |
CY62148B MoBL
Document #: 38-05039 Rev. *B
Page 4 of 11
Switching Characteristics
[5]
Over the Operating Range
62148BLL-70
Min.
Parameter
Description
Max.
Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
5.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
6.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
7.
t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
10
25
0
70
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
70
60
60
0
0
55
30
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
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| CY62148BLL-70SXC | 功能描述:IC SRAM 4MBIT 70NS 32SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類(lèi)型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán) |
| CY62148BLL-70SXI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 4M-Bit 512K x 8 70ns 32-Pin SOIC 制造商:Cypress Semiconductor 功能描述:IC SRAM 4M 5V SMD 62148 SOIC32 |
| CY62148BLL-70ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY62148BLL-70ZI | 功能描述:IC SRAM 4MBIT 70NS 32TSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類(lèi)型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán) |
| CY62148BLL-70ZIT | 制造商:Cypress Semiconductor 功能描述: |
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