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參數(shù)資料
| 型號： | CY62148-70SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 MoBL Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| 封裝： | 0.450 INCH, PLASTIC, SOIC-32 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 272K |
| 代理商： | CY62148-70SC |
CY62148CV25/30/33
MoBL
Document #: 38-05035 Rev. *A
Page 7 of 13
Switching Waveforms
Notes:
12. Device is continuously selected. OE, CE = V
IL
.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1
[12, 13]
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
SUPPLY
CURRENT
Read Cycle No. 2
[13, 14]
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE
Write Cycle No. 1 (WE Controlled)
[10, 15, 16]
17
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