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參數(shù)資料
| 型號： | CY62147V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4M (256K x 16) Static RAM |
| 中文描述： | 4分（256K × 16）靜態(tài)RAM |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 170K |
| 代理商： | CY62147V |
CY62147V MoBL
Document #: 38-05050 Rev. *A
Page 4 of 9
Data Retention Waveform
Switching Characteristics
Over the Operating Range[
6]
Parameter
Description
70 ns
Unit
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[8]
t
HZBE
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
5.
Full Device AC operation requires linear V
ramp from V
to V
> 10
μ
s or stable at V
>10
μ
s.
6.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
/I
and 30 pF load capacitance.
7.
At any given temperature and voltage condition, t
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8.
If both byte enables are toggled together this value is 10ns
9.
t
, t
, and t
are specified with C
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11.
The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[7, 9]
OE HIGH to High-Z
[9]
CE LOW to Low-Z
[7]
CE HIGH to High-Z
[7, 9]
CE LOW to Power-up
CE HIGH to Power-down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low-Z
BHE / BLE HIGH to High-Z
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
25
5
20
10
20
0
70
70
5
20
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE / BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[7, 9]
WE HIGH to Low-Z
[7]
70
60
60
0
0
40
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
10
V
CC(min.)
V
CC(min.)
t
CDR
V
DR
> 1.0 V
DATA RETENTION MODE
t
R
CE
V
CC
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|---|---|
| CY62147VLL-70ZI | 4M (256K x 16) Static RAM |
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| CY62148-55SC | 512K x 8 Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY62147V18-85BAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62147V18LL-70BAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
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| CY62147VLL-70ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4M (256K x 16) Static RAM |
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