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參數(shù)資料
| 型號： | CY62146CV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 16 Static RAM |
| 中文描述： | 256K × 16靜態(tài)RAM |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 406K |
| 代理商： | CY62146CV30 |
CY62146DV30
Document #: 38-05339 Rev. *A
Page 4 of 11
Data Retention Waveform
Capacitance
(for all packages)
[9]
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
10
10
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
Thermal Resistance
[9]
Parameter
Θ
JA
Description
Test Conditions
BGA
72
TSOP II
75.13
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
Θ
JC
8.86
8.95
°
C/W
AC Test Loads and Waveforms
[10]
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
1.5
Typ.
[5]
Max.
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
L
9
6
LL
t
CDR[9]
t
R[11]
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
t
RC
V
CC
V
CC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
V
Equivalent to:
THé ENIN EQUIVALENT
R
TH
ALL INPUT PULSES
R1
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10.Test condition for the 45 ns part is a load capacitance of 30 pF.
11.Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
μ
s or stable at V
CC(min.)
> 100
μ
s.
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
V
CC
CE
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