參數(shù)資料
型號(hào)： CY62146CV30
廠商： Cypress Semiconductor Corp.
英文描述： 256K x 16 Static RAM
中文描述： 256K × 16靜態(tài)RAM
文件頁數(shù)： 3/11頁
文件大?。?/td> 406K
代理商： CY62146CV30
CY62146DV30
Document #: 38-05339 Rev. *A
Page 3 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground
Potential......................................–0.3V to + V
CC(MAX)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
[6, 7]
.........................–0.3V to V
CC(MAX)
+ 0.3V
DC Input Voltage
[6, 7]
.....................–0.3V to V
CC(MAX)
+ 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range
Device
Range
Industrial –40°C to +85°C 2.20V to 3.60V
Ambient Tem-
perature (T
A
)
V
CC
[8]
CY62146DV30L
CY62146DV30LL
Electrical Characteristics
Over the Operating Range
Parameter Description
V
OH
Output HIGH
Voltage
Test Conditions
I
OH
= –0.1 mA V
CC
= 2.20V
I
OH
= –1.0 mA V
CC
= 2.70V
I
OL
= 0.1 mA V
CC
= 2.20V
I
OL
= 2.1 mA V
CC
= 2.70V
V
CC
= 2.2V to 2.7V
CY62146DV30-45
Min. Typ.
[5]
2.0
2.4
CY62146DV30-55
Min. Typ.
[5]
2.0
2.4
CY62146DV30-70
Min. Typ.
[5]
Max.
2.0
2.4
Unit
V
V
V
V
V
Max.
Max.
V
OL
Output LOW
Voltage
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
V
IH
Input HIGH
Voltage
1.8
1.8
1.8
V
CC
= 2.7V to 3.6V
2.2
2.2
2.2
V
V
IL
Input LOW
Voltage
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
–0.3
–0.3
–1
–0.3
–0.3
–1
–0.3
–0.3
–1
V
V
μ
A
I
IX
Input Leakage
Current
Output
Leakage
Current
V
CC
Operating
Supply
Current
Automatic
CE
Power-down
Current —
CMOS
Inputs
Automatic
CE
Power-down
Current —
CMOS Inputs
I
OZ
GND < V
O
< V
CC
, Output
Disabled
–1
+1
–1
+1
–1
+1
μ
A
I
CC
f = f
MAX
=
1/t
RC
f = 1 MHz
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
10
20
8
15
8
15
mA
1.5
3
1.5
3
1.5
3
mA
I
SB1
CE > V
CC
0.2V,
V
IN
>V
CC
–0.2V, V
IN
<0.2V)
f = f
MAX
(Address and Data
Only),
f = 0 (OE, WE, BHE and
BLE), V
CC
= 3.60V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
<
0.2V,
f = 0, V
CC
= 3.60V
L
LL
2
12
8
2
12
8
2
12
8
μ
A
I
SB2
L
LL
2
12
8
2
12
8
2
12
8
μ
A
Notes:
6. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
7. V
= V
+0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100-
μ
s ramp time from 0 to V
CC
(min) and 200
μ
s wait time after V
CC
stabilization.
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