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參數資料
| 型號： | CY62138V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 8 Static RAM |
| 中文描述： | 256K × 8靜態(tài)RAM |
| 文件頁數： | 4/9頁 |
| 文件大?。?/td> | 175K |
| 代理商： | CY62138V |
CY7C1020
4
Switching Characteristics
[4]
Over the Operating Range
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[7]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
6.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
7.
The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Description
7C1020-10
Min.
7C1020-12
Min.
7C1020-15
Min.
7C1020-20
Min.
Unit
Max.
Max.
Max.
Max.
Read Cycle Time
Address to Data Valid
10
12
15
20
ns
ns
10
12
15
20
Data Hold from Address Change
CE LOW to Data Valid
3
3
3
3
ns
ns
10
12
15
20
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
5
5
7
9
ns
ns
0
0
0
0
5
6
7
8
ns
ns
3
3
3
3
5
6
7
8
ns
ns
ns
0
0
0
0
12
12
15
20
Byte enable to Data Valid
Byte enable to Low Z
5
6
7
9
ns
ns
0
0
0
0
Byte disable to High Z
5
6
7
9
ns
Write Cycle Time
CE LOW to Write End
10
8
12
9
15
10
12
12
ns
ns
Address Set-Up to Write End
Address Hold from Write End
7
0
8
0
10
0
12
0
ns
ns
Address Set-Up to Write Start
WE Pulse Width
0
7
0
8
0
0
ns
ns
10
12
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
Byte enable to end of write
5
0
3
6
0
3
10
0
3
10
0
3
ns
ns
ns
5
6
7
9
ns
ns
7
8
9
12
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相關代理商/技術參數 |
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|---|---|
| CY62138V_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256K x 8) Static RAM |
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| CY62138VN | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:256K x 8 Static RAM |
| CY62138VNLL-70BAI | 制造商:Cypress Semiconductor 功能描述: |
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