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參數(shù)資料
| 型號： | CY62136VNLL-70BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (128K x 16) Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 7 X 7 MM, FBGA-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 569K |
| 代理商： | CY62136VNLL-70BAI |
CY62136VN MoBL
Document #: 001-06510 Rev. *A
Page 5 of 12
Switching Characteristics
Over the Operating Range
[9]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[12, 13]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC
typ., and output loading of the specified
I
/I
and 30-pF load capacitance.
10.At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
11. t
, t
, and t
are specified with C
= 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
12.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
13.The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[10]
OE HIGH to High-Z
[10, 11]
CE LOW to Low-Z
[10]
CE HIGH to High-Z
[10, 11]
CE LOW to Power-up
CE HIGH to Power-down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low-Z
[10, 11]
BLE / BHE HIGH to High-Z
[12]
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
25
25
10
10
25
25
0
0
55
25
70
35
5
5
25
25
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[10, 11]
WE HIGH to Low-Z
[10]
55
45
45
0
0
40
50
25
0
70
60
60
0
0
50
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
5
10
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62136VNLL-70BAXA | 功能描述:靜態(tài)隨機存取存儲器 SLO 3.0V SUPER LO PWR 128K X 16 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136VNLL-70BAXAT | 功能描述:靜態(tài)隨機存取存儲器 SLO 3.0V SUPER LO PWR 128K X 16 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136VNLL-70BIA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62136VNLL-70ZSXA | 功能描述:靜態(tài)隨機存取存儲器 SLO 3.0V SUPER LO PWR 128K X 16 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136VNLL-70ZSXAT | 功能描述:靜態(tài)隨機存取存儲器 SLO 3.0V SUPER LO PWR 128K X 16 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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