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參數(shù)資料
| 型號： | CY62136FV30LL-45BVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (128K x 16) Static RAM |
| 中文描述： | 128K X 16 STANDARD SRAM, 45 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 428K |
| 代理商： | CY62136FV30LL-45BVXI |
CY62136FV30 MoBL
Document Number: 001-08402 Rev. *D
Page 5 of 12
Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
Description
45 ns (Industrial)
55 ns (Automotive)
Unit
Min
Max
Min
Max
Read Cycle
t
RC
Read Cycle Time
45
55
ns
t
AA
Address to Data Valid
45
55
ns
t
OHA
Data Hold from Address Change
10
10
ns
t
ACE
CE LOW to Data Valid
45
55
ns
t
DOE
OE LOW to Data Valid
22
25
ns
t
LZOE
OE LOW to Low Z
[13]
5
5
ns
t
HZOE
OE HIGH to High Z
[13, 14]
18
20
ns
t
LZCE
CE LOW to Low Z
[13]
10
10
ns
t
HZCE
CE HIGH to High Z
[13, 14]
18
20
ns
t
PU
CE LOW to Power Up
0
0
ns
t
PD
CE HIGH to Power Down
45
55
ns
t
DBE
BLE/BHE LOW to Data Valid
22
25
ns
t
LZBE
BLE/BHE LOW to Low Z
[13]
5
10
ns
t
HZBE
Write Cycle
[15]
BLE/BHE HIGH to High Z
[13, 14]
18
20
ns
t
WC
Write Cycle Time
45
55
ns
t
SCE
CE LOW to Write End
35
40
ns
t
AW
Address Setup to Write End
35
40
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Setup to Write Start
0
0
ns
t
PWE
WE Pulse Width
35
40
ns
t
BW
BLE/BHE LOW to Write End
35
40
ns
t
SD
Data Setup to Write End
25
25
ns
t
HD
Data Hold From Write End
0
0
ns
t
HZWE
WE LOW to High Z
[13, 14]
18
20
ns
t
LZWE
WE HIGH to Low Z
[13]
10
10
ns
Notes
11. Test conditions for all parameters, other than tri-state parameters, assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input pulse
levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the
“AC Test Loads and Waveforms”
on page 4.
12.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see
application note AN13842
for further clarification.
13.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given
device.
14.t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
15.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE = V
. All signals are ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing are referenced to the edge of the signal that terminates the write.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62136FV30LL-45BVXIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 SLO 3.0V SUPER LO POWER 128Kx16 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136FV30LL-45XAKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY62136FV30LL-45ZSXA | 功能描述:靜態(tài)隨機(jī)存取存儲器 2-Mbit (128K x 16) 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136FV30LL-45ZSXAT | 功能描述:靜態(tài)隨機(jī)存取存儲器 2-Mbit (128K x 16) 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62136FV30LL45ZSXI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 2M-Bit 128K x 16 45ns 44-Pin TSOP-II |
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