參數(shù)資料
型號： CY62128EV30LL-45ZAXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 1 Mbit (128K x 8) Static RAM
中文描述： 128K X 8 STANDARD SRAM, 45 ns, PDSO32
封裝： 8 X 13.40 MM, LEAD FREE, STSOP-32
文件頁數(shù)： 3/11頁
文件大小： 861K
代理商： CY62128EV30LL-45ZAXI
Document #: 38-05579 Rev. *C
Page 3 of 11
CY62128EV30 MoBL
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Supply Voltage to Ground
Potential......................................... –0.3V to V
CC(max)
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
.........................–0.3V to V
CC(max)
+ 0.3V
DC Input Voltage
[4,5]
......................–0.3V to V
CC(max)
+ 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.....................................................> 200 mA
Operating Range
Device
Range
Ambient
Temperature
–40°C to +85°C
–40°C to +125°C
V
CC
[6]
CY62128EV30LL
Ind’l/Auto-A
Auto-E
2.2V to
3.6V
Electrical Characteristics
(Over the Operating Range)
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A)
Typ
[3]
55 ns (Auto-E)
Typ
[3]
Unit
Min
Max
Min
Max
V
OH
Output HIGH Voltage
I
OH
= –0.1 mA
I
OH
= –1.0 mA, V
CC
> 2.70V
2.0
2.0
V
2.4
2.4
V
V
OL
Output LOW Voltage
I
OL
= 0.1 mA
I
OL
= 2.1 mA, V
CC
> 2.70V
V
CC
= 2.2V to 2.7V
0.4
0.4
V
0.4
0.4
V
V
IH
Input HIGH Voltage
1.8
V
CC
+
0.3V
1.8
V
CC
+
0.3V
V
V
CC
= 2.7V to 3.6V
2.2
V
CC
+
0.3V
2.2
V
CC
+
0.3V
V
V
IL
Input LOW Voltage
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
GND < V
I
< V
CC
–0.3
0.6
–0.3
0.6
V
–0.3
0.8
–0.3
0.8
V
μ
A
μ
A
I
IX
I
OZ
I
CC
Input Leakage Current
–1
+1
–4
+4
Output Leakage Current GND < V
O
< V
CC
, Output Disabled
V
CC
Operating Supply
Current
f = 1 MHz
–1
+1
–4
+4
f = f
max
= 1/t
RC
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
11
16
11
35
mA
1.3
2.0
1.3
4.0
mA
I
SB1
Automatic CE
Power down
Current — CMOS Inputs
CE
1
> V
CC
0.2V, CE
2
< 0.2V
V
IN
> V
CC
–0.2V, V
IN
< 0.2V)
f = f
max
(Address and Data Only),
f = 0 (OE and WE), V
CC
= 3.60V
CE
1
> V
CC
– 0.2V, CE
2
< 0.2V
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
1
4
1
35
μ
A
I
SB2[7]
Automatic CE
Power down
Current — CMOS Inputs
1
4
1
30
μ
A
Capacitance
(For all packages)
[8]
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
C
IN
C
OUT
Input Capacitance
Output Capacitance
Notes:
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
= V
+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100
μ
s ramp time from 0 to V
(min) and 200
μ
s wait time after V
stabilization.
7. Only chip enables (CE
and CE
) must be at CMOS level to meet the I
/ I
spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
[+] Feedback
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