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參數(shù)資料
| 型號(hào)： | CY62128DV30L-70ZAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 1 Mb (128K x 8) Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| 封裝： | 8 X 13.40 MM, STSOP-32 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 196K |
| 代理商： | CY62128DV30L-70ZAI |
CY62128DV30
MoBL
Document #: 38-05231 Rev. *C
Page 5 of 11
Switching Characteristics
(Over the Operating Range)
[8]
Parameter
Description
CY62128DV30-55
Min.
CY62128DV30-70
Min.
Unit
Max.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW or CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[9]
OE HIGH to High Z
[9,10]
CE
1
LOW or CE
2
HIGH to Low Z
[9]
CE
1
HIGH or CE
2
LOW to High Z
[9,10]
CE
1
LOW or CE
2
HIGH to Power-up
CE
1
HIGH or CE
2
LOW to Power-down
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
70
10
10
55
25
70
35
5
5
20
25
10
10
20
25
0
0
55
70
Write Cycle Time
CE
1
LOW or CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[9,10]
WE HIGH to Low Z
[9]
55
40
40
0
0
40
25
0
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
10
10
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[12, 13]
Notes:
8.
Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of
the specified I
.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t.
10. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
11.
The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, and CE
2
= V
IH
. All signals.
12. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
13. WE is HIGH for Read cycle.
9.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62128DV30L-70ZI | 1 Mb (128K x 8) Static RAM |
| CY62128DV30L-70ZRI | 1 Mb (128K x 8) Static RAM |
| CY62128DV30LL-55SI | 1 Mb (128K x 8) Static RAM |
| CY62128DV30LL-55ZAI | 1 Mb (128K x 8) Static RAM |
| CY62128-55SC | 128K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62128DV30L-70ZI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:1-Mb (128K x 8) Static RAM |
| CY62128DV30L-70ZIT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY62128DV30L-70ZRI | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:1 Mb (128K x 8) Static RAM |
| CY62128DV30LL-55SI | 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Bulk |
| CY62128DV30LL-55SXI | 功能描述:IC SRAM 1MBIT 55NS 32SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:MoBL® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱(chēng):557-1327-2 |
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