參數(shù)資料
型號(hào): CY62128BNLL-70ZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 1-Mbit (128K x 8) Static RAM
中文描述: 128K X 8 STANDARD SRAM, 70 ns, PDSO32
封裝: 8 X 20 MM, LEAD FREE, TSOP1-32
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 589K
代理商: CY62128BNLL-70ZXC
CY62128BN
MoBL
Document #: 001-06498 Rev. *A
Page 6 of 12
Read Cycle No. 2 (OE Controlled)
[12, 13]
Write Cycle No. 1 (CE
1
or CE
2
Controlled)
[14, 15]
Notes:
13.Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
14.Data I/O is high impedance if OE = V
.
15.If CE
1
goes HIGH or CE
2
goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE
2
DATA OUT
V
CC
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
1
ADDRESS
CE
2
WE
DATA I/O
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