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參數(shù)資料
| 型號： | CY62128BNLL-70ZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1-Mbit (128K x 8) Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| 封裝： | 8 X 20 MM, LEAD FREE, TSOP1-32 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 589K |
| 代理商： | CY62128BNLL-70ZXC |
1-Mbit (128K x 8) Static RAM
CY62128BN
MoBL
Cypress Semiconductor Corporation
Document #: 001-06498 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 3, 2006
Features
Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
4.5V–5.5V operation
CMOS for optimum speed/power
Low active power
(70 ns Commercial, Industrial, Automotive-A)
— 82.5 mW (max.) (15 mA)
Low standby power
(55/70 ns Commercial, Industrial, Automotive-A)
— 110
μ
W (max.) (15
μ
A)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Available in Pb-free and non-Pb-free 32-pin (450
mil-wide) SOIC, 32-pin STSOP and 32-pin TSOP-I
Functional Description
[1]
The CY62128BN is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE
1
), an active
HIGH Chip Enable (CE
2
), an active LOW Output Enable (OE),
and tri-state drivers. This device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
1
) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
1
A
1
A
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
128K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A
A
A
A
CE2
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
18
20
24
23
22
21
25
28
27
26
Top View
SOIC
29
32
31
30
16
17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
WE
A13
A8
A9
A11
V
CC
A15
CE2
I/O7
I/O6
I/O5
I/O4
I/O3
NC
I/O0
I/O1
I/O2
G
GND
CE1
OE
A10
Pin Configuration
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62136VNLL-70BAXA | 2-Mbit (128K x 16) Static RAM |
| CY62136VN | 2-Mbit (128K x 16) Static RAM |
| CY62136VNLL-55BAI | 2-Mbit (128K x 16) Static RAM |
| CY62136VNLL-55ZSXA | 2-Mbit (128K x 16) Static RAM |
| CY62136VNLL-55ZXI | 2-Mbit (128K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62128BNLL-70ZXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (128K x 8) Static RAM |
| CY62128DV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 Mb (128K x 8) Static RAM |
| CY62128DV30_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mb (128K x 8) Static RAM |
| CY62128DV30L-55SI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 55ns 32-Pin SOIC 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- 3.0V SLOW ASYNCH SRAM - Bulk |
| CY62128DV30L-55SIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 2.5V/3.3V 1M-Bit 128K x 8 55ns 32-Pin SOIC T/R |
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