參數(shù)資料
型號： CY62127DV18LL-55ZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 1M (64K x 16) Static RAM
中文描述： 64K X 16 STANDARD SRAM, 55 ns, PDSO44
封裝： TSOP2-44
文件頁數(shù)： 3/12頁
文件大?。?/td> 384K
代理商： CY62127DV18LL-55ZI
CY62127DV30
MoBL
Document #: 38-05229 Rev. *D
Page 3 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
.........................................................................
0.3V to 3.9V
DC Voltage Applied to Outputs
in High-Z State
[5]
....................................
0.3V to V
CC
+ 0.3V
DC Electrical Characteristics
(Over the Operating Range)
DC Input Voltage
[5]
................................
0.3V to V
CC
+ 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Industrial
Ambient Temperature (T
A
)
–40°C to +85°C
V
CC
[6]
2.2V to 3.6V
Parameter
V
OH
Description
Output HIGH
Voltage
Test Conditions
2.2 < V
CC
< 2.7 I
OH
=
0.1 mA
2.7 < V
CC
< 3.6 I
OH
=
1.0 mA
2.2 < V
CC
< 2.7 I
OL
= 0.1 mA
2.7 < V
CC
< 3.6 I
OL
= 2.1 mA
2.2 < V
CC
< 2.7
CY62127DV30-45 CY62127DV30-55 CY62127DV30-70
Min. Typ.
[4]
Max. Min. Typ.
[4]
Max. Min. Typ.
[4]
Max.
2.0
2.0
2.4
2.4
0.4
0.4
1.8
V
CC
+ 0.3
2.2
V
CC
+ 0.3
0.3
0.6
0.3
0.3
0.8
0.3
1
+1
1
Unit
V
2.0
2.4
V
OL
Output LOW
Voltage
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
V
V
IH
Input HIGH
Voltage
1.8
1.8
V
2.7 < V
CC
< 3.6
2.2
2.2
V
IL
Input LOW
Voltage
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
GND < V
I
< V
CC
0.3
0.3
1
V
I
IX
Input
Leakage
Current
Output
Leakage
Current
V
CC
Operating
Supply
Current
Automatic CE
Power-down
Current—
CMOS Inputs
μ
A
I
OZ
GND < V
O
< V
CC
,
Output Disabled
1
+1
1
+1
1
+1
μ
A
I
CC
f = f
MAX
= 1/t
RC
V
CC
= 3.6V,
f = 1 MHz
I
OUT
= 0 mA,
CMOS level
6.5
0.85
13
1.5
5
10
1.5
5
10
1.5
mA
0.85
0.85
I
SB1
CE > V
CC
0.2V,
V
IN
> V
CC
0.2V, V
IN
< 0.2V,
f = f
MAX
(Address and
Data Only),
f = 0 (OE, WE, BHE and
BLE)
CE > V
CC
0.2V,
V
IN
> V
CC
0.2V or
V
IN
< 0.2V,
f = 0, V
CC
= 3.6V
L
LL
1.5
1.5
5
4
1.5
1.5
5
4
1.5
1.5
5
4
μ
A
I
SB2
Automatic CE
Power-down
Current—
CMOS Inputs
L
LL
1.5
1.5
5
4
1.5
1.5
5
4
1.5
1.5
5
4
μ
A
Notes:
5. V
=
2.0V for pulse durations less than 20 ns., V
= V
CC
+
0.75V for pulse durations less than 20 ns.
6. Full device Operation Requires linear Ramp of V
CC
from 0V to V
CC
(min) & V
CC
must be stable at V
CC
(min) for 500
μ
s.
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