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參數(shù)資料
| 型號(hào)： | CY62127DV18L-55ZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1M (64K x 16) Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 55 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 384K |
| 代理商： | CY62127DV18L-55ZI |
1 Mb (64K x 16) Static RAM
CY62127DV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05229 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 2, 2005
Features
Very high speed: 45 ns
Wide voltage range: 2.2V to 3.6V
Pin compatible with CY62127BV
Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f
MAX
Ultra-low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
Also available in Lead-Free 48-ball FBGA, and 44-lead
TSOP Type II packages
Functional Description
[1]
The CY62127DV30 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
Logic Block Diagram
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE HIGH), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH) or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
64K x 16
RAM Array
2048 x 512
I/O
0
– I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
– I/O
15
CE
WE
BHE
A
0
A
9
Power
-
Down
Circuit
BHE
BLE
CE
A
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62127DV18LL-55BVI | 1M (64K x 16) Static RAM |
| CY62127DV18LL-55ZI | 1M (64K x 16) Static RAM |
| CY62127DV30 | 1 Mb (64K x 16) Static RAM |
| CY62127DV30L | 1 Mb (64K x 16) Static RAM |
| CY62127DV30L-55BVI | 1 Mb (64K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62127DV18LL-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 Mb (64K x 16) Static RAM |
| CY62127DV18LL-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 Mb (64K x 16) Static RAM |
| CY62127DV20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Memory |
| CY62127DV20L-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1M (64K x 16) Static RAM |
| CY62127DV20L-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1M (64K x 16) Static RAM |
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