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參數(shù)資料
| 型號(hào)： | CY62126BV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 16 Static RAM |
| 中文描述： | 64K的× 16靜態(tài)RAM |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 398K |
| 代理商： | CY62126BV |
CY62126DV30
MoBL
Document #: 38-05230 Rev. *E
Page 5 of 11
Data Retention Waveform
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Characteristics
(Over the Operating Range)
[10]
Parameter
Description
CY62126DV30-45
[8]
CY62126DV30-55
CY62126DV30-70
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[13]
Read Cycle Time
45
55
70
ns
Address to Data Valid
45
55
70
ns
Data Hold from Address Change
10
10
10
ns
CE LOW to Data Valid
45
55
70
ns
OE LOW to Data Valid
OE LOW to Low Z
[11]
OE HIGH to High Z
[11,
12]
CE LOW to Low Z
[11]
CE HIGH to High Z
[11,
12]
25
25
35
ns
5
5
5
ns
15
20
25
ns
10
10
10
ns
20
20
25
ns
CE LOW to Power-up
0
0
0
ns
CE HIGH to Power-down
45
55
70
ns
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[11]
BLE/BHE HIGH to High-Z
[11,
12]
25
25
35
ns
5
5
5
ns
15
20
25
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
45
55
70
ns
CE LOW to Write End
40
40
60
ns
Address Set-up to Write End
40
40
60
ns
Address Hold from Write End
0
0
0
ns
Address Set-up to Write Start
0
0
0
ns
WE Pulse Width
35
40
50
ns
BLE/BHE LOW to Write End
40
40
60
ns
Data Set-up to Write End
25
25
30
ns
Data Hold from Write End
WE LOW to High Z
[11,
12]
WE HIGH to Low Z
[11]
0
0
0
ns
15
20
25
ns
10
10
5
ns
Notes:
10.Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
.
11. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
.
12.t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
13.The internal Write time of the memory is defined by the overlap of WE, CE = V
, BHE and/or BLE = V
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62126BVLL-55BAI | 64K x 16 Static RAM |
| CY62126BVLL-55ZI | 64K x 16 Static RAM |
| CY62126BVLL-70BAI | 64K x 16 Static RAM |
| CY62126BVLL-70ZI | 64K x 16 Static RAM |
| CY62126DV30LL-45ZSXI | Circular Connector; Body Material:Aluminum; Series:PT00; Number of Contacts:32; Connector Shell Size:18; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Pin; Insert Arrangement:18-32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62126BVLL-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62126BVLL-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62126BVLL-70BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62126BVLL-70ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62126DV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1-Mbit (64K x 16) Static RAM |
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