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參數(shù)資料
| 型號(hào)： | CY39200Z676-167MBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 8.5 ns, PBGA676 |
| 封裝： | 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676 |
| 文件頁數(shù)： | 7/57頁 |
| 文件大小： | 1166K |
| 代理商： | CY39200Z676-167MBC |
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PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 15 of 57
IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware De-
scription Language (HDL) for design entry. Warp accepts
VHDL or Verilog input, synthesizes and optimizes the entered
design, and outputs a configuration bitstream for the desired
Delta39K device. For simulation, Warp provides a graphical
waveform simulator as well as VHDL and Verilog Timing Mod-
els.
VHDL and Verilog are open, powerful, non-proprietary Hard-
ware Description Languages (HDLs) that are standards for be-
havioral design entry and simulation. HDL allows designers to
learn a single language that is useful for all facets of the design
process.
Third-Party Software
Cypress products are supported in a number of third-party de-
sign entry and simulation tools. Refer to the third-party soft-
ware data sheet or contact your local sales office for a list of
currently supported third party vendors.
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| CY39050V208-125NTXC | LOADABLE PLD, 10 ns, PQFP208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CY3930V208-125BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V208-125BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V208-125BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V208-125BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V208-125MBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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