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    參數(shù)資料
    型號(hào): CY39200V676-200NTI
    廠商: Cypress Semiconductor Corp.
    英文描述: CPLDs at FPGA Densities
    中文描述: CPLD器件在FPGA的密度
    文件頁數(shù): 61/86頁
    文件大?。?/td> 1235K
    代理商: CY39200V676-200NTI
    Delta39K ISR
    CPLD Family
    Document #: 38-03039 Rev. *H
    Page 61 of 86
    B8
    B9
    B10
    B11
    B12
    B13
    B14
    B15
    B16
    C1
    C2
    C3
    C4
    C5
    C6
    C7
    C8
    [19]
    C9
    [19]
    C10
    C11
    C12
    C13
    C14
    C15
    C16
    D1
    D2
    D3
    D4
    D5
    D6
    D7
    D8
    [19]
    D9
    [19]
    D10
    D11
    D12
    D13
    D14
    D15
    D16
    E1
    E2
    E3
    IO/V
    REF7
    NC
    V
    CCPLL
    V
    CCIO6
    IO6
    IO6
    IO6
    GND
    TDO
    IO0
    IO0
    GND
    IO7
    IO7
    V
    CCIO7
    V
    CCIO7
    NC
    IO6
    V
    CCIO6
    V
    CCIO6
    IO6
    IO6
    GND
    TDI
    IO5
    IO0
    IO0
    IO0
    GND
    IO7
    IO/V
    REF7
    IO7
    IO7
    NC
    IO6
    IO/V
    REF6
    IO6
    GND
    TCLK
    IO5
    IO5
    IO0
    IO0
    IO0
    IO/V
    REF7
    IO/VR
    EF6
    V
    CCPLL
    V
    CCIO6
    IO6
    IO6
    IO6
    GND
    TDO
    IO0
    IO0
    GND
    IO7
    IO7
    V
    CCIO7
    V
    CCIO7
    IO7
    IO6
    V
    CCIO6
    V
    CCIO6
    IO6
    IO6
    GND
    TDI
    IO5
    IO0
    IO0
    IO0
    GND
    IO7
    IO/V
    REF7
    IO7
    IO7
    IO6
    IO6
    IO/V
    REF6
    IO6
    GND
    TCLK
    IO5
    IO5
    IO0
    IO0
    IO0
    IO/V
    REF7
    IO/V
    REF6
    V
    CCPLL
    V
    CCIO6
    IO6
    IO6
    IO6
    GND
    TDO
    IO0
    IO0
    GND
    IO7
    IO7
    V
    CCIO7
    V
    CCIO7
    IO7
    IO6
    V
    CCIO6
    V
    CCIO6
    IO6
    IO6
    GND
    TDI
    IO5
    IO0
    IO0
    IO0
    GND
    IO7
    IO/V
    REF7
    IO7
    IO7
    IO6
    IO6
    IO/V
    REF6
    IO6
    GND
    TCLK
    IO5
    IO5
    IO0
    IO0
    IO0
    Table 13. 256 FBGA Pin Table
    (continued)
    Pin
    CY39030
    CY39050
    CY39100
    相關(guān)PDF資料
    PDF描述
    CY39200V676-233BBC CPLDs at FPGA Densities
    CY39200V676-233BBI CPLDs at FPGA Densities
    CY39200V676-233BGC CPLDs at FPGA Densities
    CY39200V676-233BGI CPLDs at FPGA Densities
    CY39200V676-233MBC CPLDs at FPGA Densities
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    CY39200V676-83MBXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 83MHz COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    CY39200Z208-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
    CY39200Z208-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
    CY39200Z208-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
    CY39200Z208-125BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities