參數(shù)資料
        

        


        


        
型號(hào)：
CY39200V676-200NTI

        

        
廠商：
Cypress Semiconductor Corp.

        

        
英文描述：
CPLDs at FPGA Densities

        

        
中文描述：
CPLD器件在FPGA的密度

        

        
文件頁(yè)數(shù)：
6/86頁(yè)

        

        
文件大?。?/td>
1235K

        

        
代理商：
CY39200V676-200NTI


        

        

        

	
        
    
    

    
        
	
        Delta39K ISR
        CPLD Family
        Document #: 38-03039 Rev. *H
        Page 6 of 86 
        Macrocell
        Within each logic block there are 16 macrocells. Each
        macrocell accepts a sum of up to 16 product terms from the
        product term array. The sum of these 16 product terms can be
        output in either registered or combinatorial mode.
         Figure 4
        displays the block diagram of the macrocell. The register can
        be asynchronously preset or asynchronously reset at the
        macrocell level with the separate preset and reset product
        terms. Each of these product terms features programmable
        polarity. This allows the registers to be preset or reset based
        on an AND expression or an OR expression.
        An XOR gate in the Delta39K macrocell allows for many
        different types of equations to be realized. It can be used as a
        polarity mux to implement the true or complement form of an
        equation in the product term array or as a toggle to turn the D
        flip-flop into a T flip-flop. The carry-chain input mux allows
        additional flexibility for the implementation of different types of
        logic. The macrocell can utilize the carry chain logic to
        implement adders, subtractors, magnitude comparators,
        parity tree, or even generic XOR logic. The output of the
        macrocell is either registered or combinatorial.
        Carry Chain Logic
        The Delta39K macrocell features carry chain logic which is
        used for fast and efficient implementation of arithmetic opera-
        tions. The carry logic connects macrocells in up to four logic
        blocks for a total of 64 macrocells. Effective data path opera-
        tions are implemented through the use of carry-in arithmetic,
        which drives through the circuit quickly. 
        Figure 4
         shows that
        the carry chain logic within the macrocell consists of two
        product terms (CPT0 and CPT1) from the PTA and an input
        carry-in for carry logic. The inputs to the carry chain mux are
        connected directly to the product terms in the PTA. The output
        of the carry chain mux generates the carry-out for the next
        macrocell in the logic block as well as the local carry input that
        is connected to an input of the XOR input mux. Carry-in and a
        configuration bit are inputs to an AND gate. This AND gate
        provides a method of segmenting the carry chain in any
        macrocell in the logic block.
        Macrocell Clocks
        Clocking of the register is highly flexible. Four global
        synchronous clocks (GCLK[3:0]) and a PTCLK are available
        at each macrocell register. Furthermore, a clock polarity mux
        within each macrocell allows the register to be clocked on the
        rising or the falling edge (see macrocell diagram in 
        Figure 4
        ).
        PRESET/RESET Configurations
        The macrocell register can be asynchronously preset and
        reset using the PRESET and RESET mux. Both signals are
        active high and can be controlled by either of two Preset/Reset
        product terms (PRC[1:0] in 
        Figure 4
        ) or GND. In situations
        where the PRESET and RESET are active at the same time,
        RESET takes priority over PRESET.  
        D
        Q
        PSET
        RES
        GCLK[3:0]
        PTCLK
        FROM PTM
        Up To 16 PTs
        CPT0
        CPT1
        P
        0
        1
        0
        1
        To PIM
        C
        Carry Out
        (to macrocell n+1)
        Carry In
        (from macrocell n-1)
        PRESET
        Mux
        Clock
        Polarity
        Mux
        RESET
        Mux
        Clock Mux
        Carry Chain
        Mux
        XOR Input
        Mux
        Output
        Mux
        Q
        C
        3
        3
        2
        3
        C
        C
        C
        C
        C
        C
        Figure 4. Delta39K Macrocell
        
    
        
    
    
        


        


        

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CY39200V676-233BBC
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        相關(guān)代理商/技術(shù)參數(shù)
        		

        參數(shù)描述
        		

        
        

        
CY39200V676-83MBXC
功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 83MHz COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

        

        
CY39200Z208-125BBC
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 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities

        

        
    
    
    
	
        	
    
    
     
     
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