參數(shù)資料
型號(hào): CY39050V388-181BGI
廠商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁(yè)數(shù): 51/86頁(yè)
文件大小: 1235K
代理商: CY39050V388-181BGI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 51 of 86
188
[19]
189
[19]
190
[19]
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO/V
REF7
V
CCIO7
IO7
IO7
IO7
IO7
IO/V
REF7
IO7
IO7
V
CCIO7
IO7
IO/V
REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
IO/V
REF7
V
CCIO7
IO7
IO7
IO7
IO7
IO/V
REF7
IO7
IO7
V
CCIO7
IO7
IO/V
REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
IO/V
REF7
V
CCIO7
IO7
IO7
IO7
IO7
IO/V
REF7
IO7
IO7
V
CCIO7
IO7
IO/V
REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
IO/V
REF7
V
CCIO7
IO7
IO7
IO7
IO7
IO/V
REF7
IO7
IO7
V
CCIO7
IO7
IO/V
REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
IO/V
REF7
V
CCIO7
IO7
IO7
IO7
IO7
IO/V
REF7
IO7
IO7
V
CCIO7
IO7
IO/V
REF7
IO7
IO7
IO7
GND
GCLK3
GND
GCTL3
Table 11. 208 EQFP/PQFP Pin Table
(continued)
Pin
CY39030
CY39050
CY39100
CY39165
CY39200
Table 12. 388 BGA Pin Table
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
[19]
A14
[19]
A15
A16
A17
A18
CY39050
GND
NC
IO7
IO7
IO7
IO7
IO7
NC
IO7
IO7
IO/V
REF7
IO7
IO7
IO6
IO6
GND
IO6
IO6
CY39100
GND
IO7
IO7
IO7
IO7
IO7
IO7
IO/VREF7
IO7
IO7
IO/V
REF7
IO7
IO7
IO6
IO6
GND
IO6
IO6
CY39165
GND
IO7
IO7
IO7
IO7
IO7
IO7
IO/VREF7
IO7
IO7
IO/V
REF7
IO7
IO7
IO6
IO6
GND
IO6
IO6
CY39200
GND
IO7
IO7
IO7
IO7
IO7
IO7
IO/VREF7
IO7
IO7
IO/V
REF7
IO7
IO7
IO6
IO6
GND
IO6
IO6
Note:
19. Capacitance on these I/O pins meets the PCI spec (rev. 2.2), which requires IDSEL pin in a PCI design to have capacitance less than or equal to 8 pf. In the
document titled “Delta39K CPLD Family data sheet”, this spec is defined as C
PCI.
All other I/O pins have a capacitance less than or equal to 10 pf.
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