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參數(shù)資料
| 型號： | CY37512 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 5V, 3.3V, ISR High-Performance CPLDs(5V, 3.3V, ISR 高性能CPLD) |
| 中文描述： | 為5V，3.3V，ISR的高性能CPLD的（為5V，3.3V，ISR的高性能的CPLD） |
| 文件頁數(shù)： | 8/65頁 |
| 文件大?。?/td> | 1184K |
| 代理商： | CY37512 |
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Ultra37000
CPLD Family
[1]
8
IEEE 1149.1 Compliant JTAG
The Ultra37000 family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload, Ex-
test, Idcode, and Usercode boundary scan instructions. The
JTAG interface is shown in
Figure 6
.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Development Software Support
Warp2
Warp2
is a state-of-the-art HDL compiler for designing with
Cypress programmable logic.
Warp2
utilizes a subset of IEEE
1076/1164 VHDL and IEEE 1364 as the Hardware Description
Language (HDL) for design entry.
Warp2
accepts VHDL or
Verilog input, synthesizes and optimizes the entered design,
and outputs a JEDEC map for the desired Ultra37000 device.
For simulation,
Warp2
provides a graphical waveform simula-
tor as well as VHDL and Verilog Timing Models.
VHDL and Verilog are open, powerful, non-proprietary Hard-
ware Description Languages (HDLs) that are standards for be-
havioral design entry and simulation. HDL allows designers to
learn a single language that is useful for all facets of the design
process. See the
Warp2
data sheet (CY3120 /CY3110) for fur-
ther information.
Warp3
Warp3
is a sophisticated development system that is based on
the latest version of Viewlogic
’
s CAE design environment.
Warp3
features schematic capture (ViewDraw
), VHDL and
Verilog design entry, VHDL waveform simulation (Speed-
Wave
), a VHDL debugger, and VHDL synthesis, all integrat-
ed in a graphical design environment.
Warp3
is available on
PCs using Windows
, Windows95, or Windows NT and on
Sun and Hewlett Packard workstations. See the
Warp3
data
sheet for further information.
Third-Party Software
Cypress products are supported in a number of third-party de-
sign entry and simulation tools. All major third-party software
vendors provide support for the Ultra37000 family of devices.
Refer to the third-party software data sheet or contact your
local sales office for a list of currently supported third-party
vendors.
Programming
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000
UltraISR programming cable and software. With this method,
the ISR pins of the Ultra37000 devices are routed to a connec-
tor at the edge of the printed circuit board. The 37000 UltraISR
programming cable is then connected between the parallel
port of the PC and this connector. A simple configuration file
instructs the ISR software of the programming operations to
be performed on each of the Ultra37000 devices in the system.
The ISR software then automatically completes all of the nec-
essary data manipulations required to accomplish the pro-
gramming, reading, verifying, and other ISR functions. For
more information on the Cypress ISR Interface, see the ISR
Programming Kit data sheet (CY3700i).
The second method for programming Ultra37000 devices is on
automatic test equipment (ATE). This is accomplished through
a file created by the ISR software. Check the Cypress website
for the latest ISR software download information.
The third programming option for Ultra37000 devices is to uti-
lize the embedded controller or processor that already exists
in the system. The Ultra37000 ISR software assists in this
method by converting the device JEDEC maps into the ISR
serial stream that contains the ISR instruction information and
the addresses and data of locations to be programmed. The
embedded controller then simply directs this ISR stream to the
chain of Ultra37000 devices to complete the desired reconfig-
uring or diagnostic operations. Contact your local sales office
for information on availability of this option.
The fourth method for programming Ultra37000 devices is to
use the same programmer that is currently being used to pro-
gram F
LASH
370i devices.
For all pinout, electrical, and timing requirements, refer to de-
vice data sheets. For ISR cable and software specifications,
refer to the UltraISR kit data sheet (CY3700i).
Third-Party Programmers
As with development software, Cypress support is available on
a wide variety of third-party programmers. All major third-party
programmers (including BP Micro, Data I/O, and SMS) support
the Ultra37000 family.
Figure 6. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCLK
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|---|---|
| CY37512P208-100NI | 制造商:Cypress Semiconductor 功能描述: |
| CY37512P208-100NXI | 功能描述:IC CPLD 512 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| CY37512P208-125NC | 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 125MHz 5V 208-Pin PQFP 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 125MHz CMOS Technology 5V 208-Pin PQFP |
| CY37512P208-125NXC | 功能描述:IC CPLD 512 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| CY37512P208-83NC | 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 83MHz 5V 208-Pin PQFP |
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