參數(shù)資料
型號(hào)： CY37256V
廠商： Cypress Semiconductor Corp.
英文描述： 5V, 3.3V, ISR⑩ High-Performance CPLDs
中文描述： 為5V，3.3V，ISR的⑩高性能的CPLD
文件頁(yè)數(shù)： 18/62頁(yè)
文件大?。?/td> 1796K
代理商： CY37256V
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 18 of 62
t
WH
t
IS
t
IH
t
ICO[13, 14, 15]
t
ICOL[13, 14, 15]
Synchronous Clocking Parameters
t
CO[14, 15]
t
S[13]
t
H
t
CO2[13, 14, 15]
Clock or Latch Enable Input HIGH Time
[8]
Input Register or Latch Set-up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
ns
ns
ns
ns
Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output
Set-Up Time from Input to Sync. Clk (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
0
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
0
,
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Product Term Clocking Parameters
t
COPT[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output
t
SPT
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)
t
HPT
Register or Latch Data Hold Time
t
ISPT[13]
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or
Latch Enable (PTCLK)
t
IHPT
Buried Register Used as an Input Register or Latch Data Hold Time
t
CO2PT[13, 14, 15]
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Pipelined Mode Parameters
t
ICS[13]
Input Register Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) to Output Register Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
)
Operating Frequency Parameters
f
MAX1
f
MAX2
Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(t
WL
+ t
WH
),
1/(t
S
+ t
H
), or 1/t
CO
)
[5]
f
MAX3
f
MAX4
Maximum Frequency in Pipelined Mode (Lesser of 1/(t
CO
+ t
IS
), 1/t
ICS
, 1/(t
WL
+ t
WH
), 1/(t
IS
+ t
IH
),
or 1/t
SCS
)
[5]
Reset/Preset Parameters
t
RW
t
RR[13]
t
RO[13, 14, 15]
Asynchronous Reset to Output
t
PW
t
PR[13]
t
PO[13, 14, 15]
Asynchronous Preset to Output
User Option Parameters
t
LP
Low Power Adder
t
SLEW
Slow Output Slew Rate Adder
t
3.3IO
ns
ns
ns
ns
t
SCS[13]
ns
t
SL[13]
ns
t
HL
ns
ns
ns
ns
ns
ns
ns
ns
Maximum Frequency with Internal Feedback (Lesser of 1/t
SCS
, 1/(t
S
+ t
H
), or 1/t
CO
)
[5]
MHz
MHz
Maximum Frequency with External Feedback (Lesser of 1/(t
CO
+ t
S
) or 1/(t
WL
+ t
WH
)
[5]
MHz
MHz
Asynchronous Reset Width
[5]
Asynchronous Reset Recovery Time
[5]
ns
ns
ns
ns
ns
ns
Asynchronous Preset Width
[5]
Asynchronous Preset Recovery Time
[5]
ns
ns
ns
3.3V I/O Mode Timing Adder
[5]
Switching Characteristics
Over the Operating Range
[12]
(continued)
Parameter
Description
Unit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37256VP160100AC 制造商:Cypress Semiconductor 功能描述:
CY37256VP160-100AC 制造商:Cypress Semiconductor 功能描述:
CY37256VP160-100AXC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 256 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
CY37256VP160100AXI 制造商:Cypress Semiconductor 功能描述:
CY37256VP160-100AXI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 256 Macrocell 5V IND RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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