參數(shù)資料
型號(hào): CY74FCT138TLCC
廠商: Texas Instruments, Inc.
英文描述: 1-of-8 Decoder
中文描述: 1 - 8解碼器
文件頁數(shù): 1/6頁
文件大小: 155K
代理商: CY74FCT138TLCC
1-of-8 Decoder
fax id: 7013
CY54/74FCT138T
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
May 1994 – Revised March 17, 1997
408-943-2600
1CY54/74FCT138T
Features
Function, pinout, and drive compatible with FCT and
F logic
FCT-C speed at 5.0 ns max. (Com’l),
FCT-A speed at 5.8 ns max. (Com’l)
Reduced V
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
ESD > 2000V
Matched rise and fall times
Fully compatible with TTL input and output logic levels
Extended commercial range of
40°C to +85°C
Sink current
64 mA (Com’l),
32 mA (Mil)
Source current
32 mA (Com’l),
12 mA (Mil)
Dual 1-of-8 decoder with enables
Functional Description
The FCT138T is a 1-of-8 decoder. The FCT138T accepts
three binary weighted inputs (A
0
, A
1
, A
2
) and, when enabled,
provides eight mutually exclusive active LOW outputs
(O
0
–O
7
). The FCT138T features three enable inputs, two
active LOW (E
1
, E
2
) and one active HIGH (E
3
).
All inputs will be HIGH unless E
1
and E
2
are LOW and E
3
is
HIGH. This multiple enable function allows easy parallel
expansion of the device to a 1-of-32 (5 lines to 32 lines)
decoder with just four FCT138T devices and one inverter.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Pin Description
Name
A
E
1
E
2
E
3
O
Description
Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
A
1
A
2
E
1
E
2
E
3
O
7
V
CC
O
0
O
1
O
2
O
3
GND
FCT138T–2
Top View
4
8
9
10
11
12
13
7
6 5
15 16 17 18
3
2
1
20
19
14
E
E
E
O2
O4
O
5
O1
O
6
NC
A
1
A
0
NC
N
N
V
CC
O
0
O
7
GND
O3
Top View
DIP/SOIC/QSOP
A
LCC
16
15
14
13
12
11
10
9
O
4
O
5
O
6
O
7
O
0
O
1
O
2
O
3
E
1
A
2
A
1
A
0
E
2
E
3
FCT138T–1
A
0
O
4
O
5
O
6
FCT138T–3
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