參數(shù)資料
型號: CY37064VP44-143JC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 5V, 3.3V, ISR⑩ High-Performance CPLDs
中文描述: EE PLD, 8.5 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 6/62頁
文件大?。?/td> 1782K
代理商: CY37064VP44-143JC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 6 of 62
f
Figure 2. I/O and Buried Macrocells
Figure 3. Input Macrocell
C2
C3
DECODE
C2
C3
DECODE
0
1
2
3
O
C6 C5
“0”
“1”
0
1
O
D/T/L
Q
R
P
0
1
2
3
4
O
C0
0
1
O
C4
FEEDBACK TO PIM
FEEDBACK TO PIM
BLOCK RESET
ASYNCHRONOUS
0
16
TERMS
I/O MACROCELL
I/O CELL
FROM PTM
0
1
O
D/T/L
Q
R
P
FROM PTM
0
16
PRODUCT
1
O
C7
FEEDBACK TO PIM
BURIED MACROCELL
0
ASYNCHRONOUS
PRODUCT
TERMS
C1
0
1
2
3
4
Q
C24
C0 C1C24
C25
C25
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
BLOCK PRESET
FAST
SLOW
C26
SLEW
0
1
0
1
0
1
0
1
OE0 OE1
0
1
2
3
O
C12 C13
TO PIM
D
Q
D
Q
D
Q
LE
INPUT PIN
0
1
2
3
O
C10
FROM CLOCK
POLARITY MUXES
C11
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