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參數(shù)資料
| 型號(hào)： | CY37064VP44-143JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 5V, 3.3V, ISR⑩ High-Performance CPLDs |
| 中文描述： | EE PLD, 8.5 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 17/62頁(yè) |
| 文件大小： | 1782K |
| 代理商： | CY37064VP44-143JC |
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 17 of 62
3.3V AC Test Loads and Waveforms
295
(COM’L)
393
(MIL)
AC Characteristics
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
<2 ns
OUTPUT
340
(COM’L)
453
(MIL)
Equivalent to:
THéVENIN EQUIVALENT
158
(COM’L)
1.77V (COM'L)
1.77V (MIL)
295
(COM'L)
393
(MIL)
340
(COM'L)
453
(MIL)
<2 ns
(c)
270
(MIL)
5 OR 35 pF
Parameter
[11]
t
ER(–)
V
X
1.5V
Output Waveform—Measurement Level
t
ER(+)
2.6V
t
EA(+)
1.5V
t
EA(–)
V
the
(d) Test Waveforms
V
OH
V
X
0.5V
V
OL
V
X
0.5V
V
X
V
OH
0.5V
V
X
V
OL
0.5V
Switching Characteristics
Over the Operating Range
[12]
Parameter
Combinatorial Mode Parameters
t
PD[13, 14, 15]
t
PDL[13, 14, 15]
t
PDLL[13, 14, 15]
t
EA[13, 14, 15]
t
ER[11, 13]
Input Register Parameters
t
WL
Notes:
11.
t
measured with 5-pF AC Test Load and t
measured with 35-pF AC Test Load.
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add t
to this spec.
14. Outputs using Slow Output Slew Rate, add t
SLEW
to this spec.
15. When V
CCO
= 3.3V, add t
3.3IO
to this spec.
Description
Unit
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
Input to Output Disable
ns
ns
ns
ns
ns
Clock or Latch Enable Input LOW Time
[8]
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| CY37064VP48-143BAC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
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