- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1992 > CY2SSTV855ZXI (Silicon Laboratories Inc)IC CLOCK DIFFDRV PLL DDR 28TSSOP PDF資料下載
參數(shù)資料
| 型號： | CY2SSTV855ZXI |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFFDRV PLL DDR 28TSSOP |
| 標準包裝： | 50 |
| 系列： | * |
| 類型： | * |
| PLL： | * |
| 主要目的： | * |
| 輸入： | * |
| 輸出： | * |
| 電路數(shù)： | * |
| 比率 - 輸入:輸出： | * |
| 差分 - 輸入:輸出： | * |
| 頻率 - 最大： | * |
| 電源電壓： | * |
| 工作溫度： | * |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
Differential Clock Buffer/Driver
CY2SSTV855
......................... Document #: 38-07459 Rev. *F Page 1 of 6
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
Features
Phase-locked loop (PLL) clock distribution for Double
Data Rate Synchronous DRAM applications
1:5 differential outputs
External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
SSCG: Spread Aware for electromagnetic
interference (EMI) reduction
28-pin TSSOP package
Conforms to JEDEC DDR specifications
Functional Description
The CY2SSTV855 is a high-performance, very-low-skew,
very-low-jitter zero-delay buffer that distributes a differential
clock input pair (SSTL_2) to four differential (SSTL_2) pairs of
clock outputs and one differential pair of feedback clock
outputs. In support of low power requirements, when
power-down is HIGH, the outputs switch in phase and
frequency with the input clock. When power-down is LOW, all
outputs are disabled to a high-impedance state and the PLL is
shut down.
The device supports a low-frequency power-down mode.
When the input is < 20 MHz, the PLL is disabled and the
outputs are put in the Hi-Z state. When the input frequency is
> 20 MHz, the PLL and outputs are enabled.
When AVDD is tied to ground, the PLL is turned off and
bypassed with the input reference clock gated to the outputs.
The Cypress CY2SSTV855 is Spread Aware and supports
tracking of Spread Spectrum clock inputs to reduce EMI
Block Diagram
Pin Configuration
28-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
YT3
VDDQ
FBOUTT
YT2
YC2
GND
VDDQ
FBOUTC
YC3
VDDQ
PWRDWN
FBINT
FBINC
GND
YT0
VDDQ
AGND
YT1
YC1
GND
VDDQ
AVDD
YC0
VDDQ
GND
CLKINT
CLKINC
CY2S
STV855
FBOUTT
FBOUTC
YT0
YC0
YC3
YT3
PLL
PWRDWN
YC2
YT2
YT1
YC1
Powerdown
and test
logic
AVDD
CLKINT
CLKINC
FBINT
FBINC
相關PDF資料 |
PDF描述 |
|---|---|
| CY2SSTV857ZXI-27 | IC CLK DDR266/333BUF1:10 48TSSOP |
| CY2SSTV857ZXI-32 | IC CLK DDR266/333BUF1:10 48TSSOP |
| CY505YC64DT | IC CLK CK505 BROADWATER 64TSSOP |
| CYW150OXC | IC CLOCK 440BX AGP 56SSOP |
| CYW173SXC | IC CLK GEN TAPE DRV 4CH 16SOIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY2SSTV855ZXIT | 功能描述:時鐘緩沖器 DDR1 Clock PLL RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2SSTV857 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver DDR333/PC2700-Compliant |
| CY2SSTV857-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clocks and Buffers |
| CY2SSTV857-32 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant |
| CY2SSTV8575 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復。