參數(shù)資料
型號: CY29948AIT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
中文描述: 29948 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32
文件頁數(shù): 4/7頁
文件大?。?/td> 108K
代理商: CY29948AIT
CY29948
Document #: 38-07288 Rev. *B
Page 4 of 7
Notes:
6.
7.
8.
9.
10. See
11.
Part-to-Part skew at a given temperature and voltage.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
Outputs driving 50
transmission lines.
50% input duty cycle.
Figures
2 and 3
.
AC Parameters
[6]
:
V
DD
= V
DDC
= 3.3V ±10% or 2.5V ±5%, Over the specified operating range
Parameter
Fmax
Description
Conditions
Min.
Typ.
Max.
200
170
8.0
8.9
10.0
10.9
55
10
10
250
1.5
2.0
Unit
MHz
Input Frequency
[7]
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
Tpd
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
[7]
PECL_CLK to Q Delay
[7]
TCLK to Q Delay
[7]
Output Duty Cycle
[7, 8, 9]
Output Enable Time (all outputs)
Output Disable Time (all outputs)
Output-to-Output Skew
[7, 9]
Part-to-Part Skew
[11]
4.0
4.4
6.0
6.4
45
2
2
ns
V
DD
= 2.5V
FoutDC
tpZL, tpZH
tpLZ, tpHZ
Tskew
Tskew(pp)
Measured at V
DD
/2
%
ns
ns
ps
ns
150
PECL_CLK to Q
TCLK to Q
SYNC_OE to PECL_CLK
SYNC_OE to TCLK
PECL_CLK to SYNC_OE
TCLK to SYNC_OE
0.8V to 2.0V, V
DD
= 3.3V
0.6V to 1.8V, V
DD
= 2.5V
Ts
Set-up Time
[7, 10]
1.0
0.0
0.0
1.0
0.20
0.20
ns
Th
Hold Time
[7, 10]
ns
Tr/Tf
Output Clocks Rise/Fall Time
[9]
1.0
1.3
ns
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
R
T
= 50 ohm
R
T
= 50 ohm
CY29948 DUT
Figure 2. LVCMOS_CLK CY29948 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
R
T
= 50 ohm
CY29948 DUT
Zo = 50 ohm
R
T
= 50 ohm
VTT
Figure 3. PECL_CLK CY29948 Test Reference for V
CC
= 3.3V and V
CC
= 2.5V
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