參數(shù)資料
型號: CY29940AI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
中文描述: 29940 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-32
文件頁數(shù): 3/7頁
文件大?。?/td> 189K
代理商: CY29940AI
CY29940
Document #: 38-07283 Rev. *B
Page 3 of 7
Maximum Ratings
[2]
Maximum Input Voltage Relative to V
SS
:............. V
SS
0.3V
Maximum Input Voltage Relative to V
DD
:.............V
DD
+ 0.3V
Storage Temperature: ................................
65
°
C to + 150
°
C
Operating Temperature:................................
40
°
C to +85
°
C
Maximum ESD Protection...............................................2 kV
Maximum Power Supply:................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
or V
DD
).
Notes:
2.
3.
4.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Inputs have pull-up/pull-down resistors that effect input current.
The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the
High
input is within the VCMR
range and the input lies within the VPP specification. Driving series or parallel terminated 50
(or 50
to VDD/2) transmission lines
Outputs driving 50
transmission lines.
See
Figure 1
&2.
50% input duty cycle.
5.
6.
7.
DC Parameters:
V
DD
= 3.3V ±5% or 2.5V ±5%, V
DDC
= 3.3V ±5% or 2.5V ±5%, T
A
=
40
°
C to +85
°
C
Parameter
V
IL
V
IH
I
IL
I
IH
V
PP
Description
Conditions
Min.
V
SS
2.0
Typ.
Max.
0.8
V
DD
200
200
1000
Unit.
V
V
μA
μA
mV
Input Low Voltage
Input High Voltage
Input Low Current
[3]
Input High Current
[3]
Peak-to-Peak Input
Voltage
PECL_CLK
Common Mode Range
[4]
PECL_CLK
500
V
CMR
V
DD
= 3.3V
V
DD
= 2.5V
I
OL
= 20 mA
I
OH
=
20 mA, V
DDC
= 3.3V
I
OH
=
20 mA, V
DDC
= 2.5V
V
DD
1.4
V
DD
1.0
V
DD
0.6
V
DD
0.6
0.5
V
V
V
V
V
V
OL
V
OH
Output Low Voltage
[5, 6, 7]
Output High Voltage
[5, 6, 7]
2.4
1.8
I
DDQ
Quiescent Supply
Current
Dynamic Supply
Current
5
7
mA
I
DD
V
DD
= 3.3V, Outputs @
150 MHz, CL=15 pF
V
DD
= 3.3V, Outputs @
200 MHz, CL=15 pF
V
DD
= 2.5V, Outputs @
150 MHz, CL=15 pF
V
DD
= 2.5V, Outputs @
200 MHz, CL=15 pF
V
DD
= 3.3V
V
DD
= 2.5V
285
mA
335
200
240
Z
out
Output Impedance
8
10
12
15
4
16
20
C
in
Input Capacitance
pF
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