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參數(shù)資料
| 型號： | CY29949 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer |
| 中文描述： | 2.5V或3.3V 200兆赫一時15分時鐘分配緩沖區(qū) |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 111K |
| 代理商： | CY29949 |
2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer
CY29949
Cypress Semiconductor Corporation
Document #: 38-07289 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised November 6, 2003
Features
2.5V or 3.3V operation
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS-/LVTTL-compatible outputs
15 clock outputs: drive up to 30 clock lines
1X and 1/2X configurable outputs
Output three-state control
350 ps max. output-to-output skew
Pin compatible with MPC949, MPC9449
Available in Commercial and Industrial temp. range
52-pin TQFP package
Description
The CY29949 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL
or LVCMOS/LVTTL compatible input clocks. These clock
sources can be used to provide for test clocks as well as the
primary system clocks. All other control inputs are
LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or
LVTTL compatible and can drive 50
series or parallel termi-
nated transmission lines. For series terminated transmission
lines, each output can drive one or two traces giving the device
an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:D) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the
MR/OE# input. When MR/OE# is set HIGH, it resets the
internal flip-flops and three-states the outputs.
Block Diagram
Pin Configuration
MR/OE#
TCLK_SEL
VDD
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
VSS
N
V
Q
V
Q
V
Q
V
Q
V
Q
V
N
N
V
Q
V
Q
V
Q
V
V
Q
V
Q
V
NC
VSS
QC0
VDDC
QC1
VSS
QC2
VDDC
QC3
VSS
VSS
QD5
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29949
0
1
1
2
0
1
1
2
0
1
0
1
DSELA
DSELB
DSELC
DSELD
MR/OE#
1
2
1
2
0
1
0
1
2
3
4
6
QA(0:1)
QB(0:2)
QC(0:3)
QD(0:5)
PECL_SEL
TCLK_SEL
PECL_CLK
R
R
R
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY29949AC | 2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer |
| CY29949ACT | 2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer |
| CY29949AI | 2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer |
| CY29949AIT | 2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer |
| CY29FCT520CTSOCT | Multi-Level Pipeline Register |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY29949_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer |
| CY29949AC | 制造商:Cypress Semiconductor 功能描述:Clock Divider 3-IN LVCMOS/LVTTL 52-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:2.5/3.3,200MHZ,1:15LVPECL/LVCMOS IN LVCMOS OUT BUF - Bulk |
| CY29949ACT | 制造商:Cypress Semiconductor 功能描述:Clock Divider 3-IN LVCMOS/LVTTL 52-Pin TQFP T/R |
| CY29949AI | 制造商:Cypress Semiconductor 功能描述:Clock Divider 3-IN LVCMOS/LVTTL 52-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:TIMING DEVICE - Bulk |
| CY29949AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer |
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