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參數(shù)資料
| 型號： | CY28447LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 22/22頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 72QFN |
| 標(biāo)準(zhǔn)包裝： | 240 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
CY28447
........................ Document #: 38-07724 Rev *C Page 9 of 22
The CY28447 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28447 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Byte 12: Control Register 12
Bit
@Pup
Name
Description
7
0
CLKREQ#9
CLKREQ#9 Input Enable
0 = Disable 1 = Enable
6
0
CLKREQ#8
CLKREQ#8 Input Enable
0 = Disable 1 = Enable
5
0
CLKREQ#7
CLKREQ#7 Input Enable
0 = Disable 1 = Enable
4
0
CLKREQ#6
CLKREQ#6 Input Enable
0 = Disable 1 = Enable
3
0
CLKREQ#5
CLKREQ#5 Input Enable
0 = Disable 1 = Enable
2
0
CLKREQ#4
CLKREQ#4 Input Enable
0 = Disable 1 = Enable
1
0
CLKREQ#3
CLKREQ#3 Input Enable
0 = Disable 1 = Enable
0
CLKREQ#2
CLKREQ#2 Input Enable
0 = Disable 1 = Enable
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
0
CLKREQ#1
CLKREQ#1 Input Enable
0 = Disable 1 = Enable
6
1
LCD 96_100M Clock
Speed
LCD 96_100M Clock Speed
0 = 96 MHz 1 = 100 MHz
5
1
RESERVED
RESERVED, Set = 1
4
1
RESERVED
RESERVED, Set = 1
3
1
PCI4
PCI4 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
2
1
PCI3
PCI3 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
1
PCI2
PCI2 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
0
1
PCI1
PCI1 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28447LFXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Calistoga System Clk Extra SRC Output RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28506OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR MOTHERBOARDS - Bulk |
| CY28506OCT | 制造商:Rochester Electronics LLC 功能描述:CLOC - Tape and Reel |
| CY28507ZC-3 | 功能描述:時鐘緩沖器 PacketClockClk RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28508OCT | 制造商:Cypress Semiconductor 功能描述: |
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