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參數(shù)資料
| 型號： | CY28441ZXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Clock Generator for Intel Alviso Chipset |
| 中文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 261K |
| 代理商： | CY28441ZXCT |
CY28441
Document #: 38-07679 Rev. **
Page 2 of 20
Pin Description
Pin No.
33, 32
Name
Type
I, PU
Description
CLKREQA#,
CLKREQB#,
3.3V LVTTL input for enabling assigned SRC clock, active LOW
. CLKREQA#
defaults to enable/disable SRCT/C4, CLKREQB# defaults to enable/disable
SRCT/C5. Assignment can be changed via SMBUS register Byte 8.
3.3V LVTTL input for CPU_STP# active LOW
.
O, DIF
Differential CPU clock outputs
.
O, DIF
Selectable differential CPU or SRC clock output
.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
O, DIF
Fixed 96-MHz clock output
.
I/O, SE
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output
.
Refer to DC Electrical Specifications table for
V
IL_FS
,V
IH_FS
specifications.
I
3.3V-tolerant input for CPU frequency selection
.
Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z, 1 = Ref/N
Refer to DC Electrical Specifications table for
V
IL_FS
,V
IH_FS
specifications.
I
3.3V-tolerant input for CPU frequency selection
.
Selects test mode if pulled
to greater than 2.0V when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for
V
IL_FS
,V
IH_FS
specifications.
I
A precision resistor is attached to this pin
, which is connected to the internal
current reference.
O, SE
33-MHz clocks
.
I, PU
3.3V LVTTL input for PCI_STP# active LOW
.
I/O, SE
33-MHz clock/CPU2 select
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
O, SE
33-MHz clock
.
O, SE
Reference clock
. 3.3V 14.318-MHz clock output.
I
SMBus-compatible SCLOCK
.
I/O
SMBus-compatible SDATA
.
O, DIF
Differential serial reference clock
. Recommended output for SATA.
54
44, 43, 41, 40 CPUT/C
36, 35
CPU_STP#
I, PU
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
14, 15
12
DOT96T, DOT96C
FS_A/USB_48
16
FS_B/TEST_MODE
53
FS_C/TEST_SEL
39
IREF
56, 3, 4, 5
55
8
PCI
PCI_STP#
PCIF0/ITP_EN
9
52
46
47
26, 27
PCIF1
REF
SCLK
SDATA
SRC4_SATAT,
SRC4_SATAC
SRCT/C
24, 25, 22,
23, 19, 20,
17, 18, 31, 30
11
42
1,7
48
21, 28, 34
37
13
45
2,6
51
29
38
10
O, DIF
Differential serial reference clocks
.
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
I
3.3V power supply for outputs
.
3.3V power supply for outputs
.
3.3V power supply for outputs
.
3.3V power supply for outputs
.
3.3V power supply for outputs
.
3.3V power supply for PLL
.
Ground for outputs
.
Ground for outputs
.
Ground for outputs
.
Ground for outputs
.
Ground for outputs
.
Ground for PLL
.
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs
. After VTT_PWRGD#
(active LOW) assertion, this pin becomes a real-time input for asserting
power-down (active HIGH).
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PDF描述 |
|---|---|
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28442 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28442-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28442-2_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28442ZXC | 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY28442ZXC-2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Calistoga RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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