參數(shù)資料
型號： CY28410
廠商： Cypress Semiconductor Corp.
英文描述： Clock Generator for Intel Grantsdale Chipset
中文描述： 時(shí)鐘發(fā)生器英特爾Grantsdale芯片
文件頁數(shù)： 4/18頁
文件大?。?/td> 281K
代理商： CY28410
CY28410
Document #: 38-07593 Rev. *C
Page 4 of 18
Control Registers
....
....
....
....
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
46:39
47
55:48
56
....
....
....
....
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Description
Byte Read Protocol
Description
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Table 3. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Description
Block Read Protocol
Description
Bit
Bit
Byte 0:Control Register 0
Bit
7
@Pup
1
Name
Description
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
SRC[T/C]6
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Reserved, Set = 1
6
1
5
1
SRC[T/C]5
4
1
SRC[T/C]4
3
1
SRC[T/C]3
2
1
SRC[T/C]2
1
1
SRC[T/C]1
0
1
Reserved
相關(guān)PDF資料
PDF描述
CY28410ZXC Paired Cable; Number of Conductors:24; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:12; Conductor Material:Copper; Features:Traditional Analog Audio Applications RoHS Compliant: Yes
CY28410OC Hook-Up Wire; Conductor Size AWG:22; No. Strands x Strand Size:7 x 30; Jacket Color:Gray; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes
CY28410ZC Clock Generator for Intel Grantsdale Chipset
CY28410ZCT Clock Generator for Intel Grantsdale Chipset
CY28410OCT Clock Generator for Intel Grantsdale Chipset
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28410-2 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset
CY284108OXC 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Server, CK410B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CY284108OXCT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Server, CK410B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CY284108ZXC 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Server, CK410B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CY284108ZXCT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Server, CK410B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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