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參數(shù)資料
| 型號(hào)： | CY28409ZCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Clock Synthesizer with Differential SRC and CPU Outputs |
| 中文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, MO-153, TSSOP-56 |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 330K |
| 代理商： | CY28409ZCT |
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CY28409
Document #: 38-07445 Rev. *B
Page 10 of 18
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
rising edges of the internal CPUT clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal
will not be driven. Due to the external pull-down circuitry,
CPUC will be LOW during this stopped state.
CPU_STP# Deassertion
The de-assertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPU Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 6. CPU_STP# Deassertion Waveform
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| CY28409OCT | Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409ZC | RF/Coaxial Connector; RF Coax Type:UHF; Contact Termination:Solder; Body Style:Straight Plug; RG Cable Type:8, 9, 87A, 213, 214, 225; Body Plating:Nickel RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28409ZXC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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| CY28410 | 制造商:SPECTRALINEAR 制造商全稱(chēng):SPECTRALINEAR 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410-2 | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset |
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