參數(shù)資料
型號: CY28409ZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: RF/Coaxial Connector; RF Coax Type:UHF; Contact Termination:Solder; Body Style:Straight Plug; RG Cable Type:8, 9, 87A, 213, 214, 225; Body Plating:Nickel RoHS Compliant: Yes
中文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6 X 12 MM, MO-153, TSSOP-56
文件頁數(shù): 1/18頁
文件大小: 330K
代理商: CY28409ZC
Clock Synthesizer with Differential SRC and CPU Outputs
CY28409
Cypress Semiconductor Corporation
Document #: 38-07445 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 26, 2003
Features
Supports Intel
Pentium
4-type CPUs
Selectable CPU frequencies
3.3V power supply
Ten copies of PCI clocks
Five copies of 3V66 with one optional VCH
Two copies 48-MHz USB clocks
Three differential CPU clock pairs
One differential SRC clock
I
2
C support with readback capabilities
Ideal Lexmark Spread Spectrum profile for maximum
EMI reduction
56-pin SSOP and TSSOP packages
Note:
1.
Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
CPU
SRC
3V66
PCI
REF
48M
x 3
x 1
x 5
x 10
x 2
x 2
Block Diagram
Pin Configuration
REF_0
REF_1
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PCI6
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
3V66_2
3V66_3
SCLK
FS_B
VDD_A
VSS_A
SDATA
3V66_4/VCH
VDD_SRC
VTT_PWRGD#
VDD_48
VSS_48
DOT_48
SRCT
SRCC
VSS_SRC
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
VSS_CPU
CPUT2
CPUC2
VDD_CPU
CPU_STP#
PCI_STP#
FS_A
VSS_IREF
IREF
USB_48
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
~
VDD_REF
REF0:1
XTAL
OSC
PLL Ref Freq
XOUT
XIN
VDD_PCI
PCIF[0:2]
SCLK
PLL1
I
2
C
Logic
VDD_48MHz
DOT_48
USB_48
SDATA
VDD_3V66
3V66_[0:3]
Divider
Network
VDD_CPU
CPUT[0:2], CPUC[0:2]
FS_[A:B]
VTT_PWRGD#
PD#
IREF
PCI[0:6]
3V66_4/VCH
2
PLL2
VDD_SRC
SRCT, SRCC
CPU_STP#
PCI_STP#
VDD_REF
C
56 SSOP/TSSOP
[1]
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CY28409ZCT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs
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