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參數(shù)資料
| 型號： | CY28409ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | RF/Coaxial Connector; RF Coax Type:UHF; Contact Termination:Solder; Body Style:Straight Plug; RG Cable Type:8, 9, 87A, 213, 214, 225; Body Plating:Nickel RoHS Compliant: Yes |
| 中文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 330K |
| 代理商： | CY28409ZC |
CY28409
Document #: 38-07445 Rev. *B
Page 11 of 18
PCI_STP# Assertion
[2]
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
). (See
Figure 7
.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Note:
2.
The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 7. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F
PCI
SRC 100MHz
Tsu
Tdrive_SRC
Figure 8. PCI_STP# Deassertion Waveform
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28409ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409ZXC | 功能描述:時(shí)鐘合成器/抖動清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28409ZXCT | 功能描述:時(shí)鐘合成器/抖動清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28410 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset |
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