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參數(shù)資料
| 型號： | CY28409OCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Clock Synthesizer with Differential SRC and CPU Outputs |
| 中文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 330K |
| 代理商： | CY28409OCT |
CY28409
Document #: 38-07445 Rev. *B
Page 8 of 18
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is
not true
.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe.........................................Actual loading seen by crystal
using standard value trim capacitors
Ce.....................................................External trim capacitors
Cs..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
PD# (Power-down) Clarification
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so as not to cause glitches
while changing to the low ‘stopped’ state.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of
the CPUC clock then all clock outputs (except CPU) clocks
must be held low on their next high to low transition. CPU
clocks must be held with CPU clock pin driven high with a
value of 2 x Iref and CPUC undriven. Due to the state of
internal logic, stopping and holding the REF clock outputs in
the LOW state may require more than one clock cycle to
complete
Figure 1. Crystal Capacitive Clarification
X T A L
C e2
C e1
C s1
C s2
X1
X 2
C i1
C i2
C lock C hip
(C Y 28409)
T race
2.8pF
T rim
33pF
P in
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Ce
= 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
=
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
CLe
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28409ZC | RF/Coaxial Connector; RF Coax Type:UHF; Contact Termination:Solder; Body Style:Straight Plug; RG Cable Type:8, 9, 87A, 213, 214, 225; Body Plating:Nickel RoHS Compliant: Yes |
| CY28410 | Clock Generator for Intel Grantsdale Chipset |
| CY28410ZXC | Paired Cable; Number of Conductors:24; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:12; Conductor Material:Copper; Features:Traditional Analog Audio Applications RoHS Compliant: Yes |
| CY28410OC | Hook-Up Wire; Conductor Size AWG:22; No. Strands x Strand Size:7 x 30; Jacket Color:Gray; Approval Bodies:UL; Approval Categories:UL AWM Style 1213; Passes VW-1 Flame Test; Cable/Wire MIL SPEC:MIL-W-16878/4 Type E RoHS Compliant: Yes |
| CY28410ZC | Clock Generator for Intel Grantsdale Chipset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28409OCXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409OXC | 功能描述:時鐘合成器/抖動清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28409OXCT | 功能描述:時鐘合成器/抖動清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28409ZC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409ZCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
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