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參數(shù)資料
| 型號： | CY28408ZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | TV 19C 19#12 SKT RECP |
| 中文描述： | 166 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 14 MM, TSSOP2-56 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CY28408ZC |
CY28408
Document #: 38-07617 Rev. **
Page 4 of 19
19
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
27:20
28
29
27:21
28
29
37:30
38
39
Byte 0: CPU Clock Register
[2]
Bit
@Pup
Name
Description
7
0
Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
CPU clock Power-down Mode Select. 0 = Drive CPUT to 4 or 6 IREF and
drive CPUC to low when PD# is asserted LOW. 1 = Three-state all CPU
outputs. This is only applicable when PD# is LOW. It is not applicable to
CPU_STP#.
3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
Reflects the current value of the external CPU_STP#. This bit is Read-only.
Reflects the current value of the internal PCI_STP# function when read.
Internally PCI_STP# is a logical AND function of the internal SMBus register
bit and the external PCI_STP# pin. This is a Read and Write control bit.
Frequency Select Bit 2. Reflects the value of SEL2. This bit is Read-only.
Frequency Select Bit 1. Reflects the value of SEL1. This bit is Read-only.
Frequency Select Bit 0. Reflects the value of SEL0. This bit is Read-only.
6
0
5
0
3V66_1/VCH
4
Pin 53
CPU_STP#
3
Pin 34
PCI_STP#
2
1
0
Pin 40
Pin 55
Pin 54
SEL2
SEL1
SEL0
Byte 1: CPU Clock Register
Bit
7
@Pup
Pin 43
Name
Description
MULT0 Value. This bit is Read-only.
Controls functionality of CPUT/C outputs when CPU_STP# is asserted. 0
= Drive CPUT to 4 or 6 IREF and drive CPUC to low when CPU_STP# is
asserted LOW. 1 = Tri-state all CPU outputs when CPU_STP# is
asserted.This bit will override Byte0, Bit6 such that even if it is a 0, when
PD# goes low the CPU outputs will be tri-stated.
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
Controls CPUT0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
CPUT/C2 Output Control
1 = enabled, 0 = three-state CPUT/C2
This is a Read and Write control bit.
6
0
5
0
4
0
3
0
2
1
CPUT/C2
Note:
2. PU = Internal Pull-up. PD = Internal Pull-down. T = Tri-level logic input.
Table 4. Byte Read and Byte Write Protocol
(continued)
Byte Write Protocol
Description
Byte Read Protocol
Description
Bit
Bit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28408ZCT | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TVS01; Number of Contacts:3; Connector Shell Size:9; Connecting Termination:Crimp; Circular Shell Style:Straight Receptacle; Body Style:Straight |
| CY28409 | Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409ZCT | Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409OC | RF/Coaxial Connector; RF Coax Type:BNC; Contact Termination:Clamp; Body Style:Straight Plug; RG Cable Type:59, 62, 71, 140, 210, 302 RoHS Compliant: Yes |
| CY28409OCT | Clock Synthesizer with Differential SRC and CPU Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28408ZCT | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential CPU Outputs |
| CY28409 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409_06 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409AZXC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28409AZXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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