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參數(shù)資料
| 型號： | CY28405OCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Circular Connector; No. of Contacts:6; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-6 |
| 中文描述： | 200.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 259K |
| 代理商： | CY28405OCT |
CY28405
Document #: 38-07512 Rev. *B
Page 2 of 19
Pin Description
Pin No.
1, 2
1, 2, 7, 8, 9 FS_A, FS_B, FS_C,
FS_D, FS_E
4
XIN
Name
Type
O, SE
I
Description
REF(0:1)
Reference Clock
.
3.3V 14.318-MHz clock output.
3.3V LVTTL latched input for CPU frequency selection
.
I
Crystal Connection or External Reference Frequency Input
. This pin
has dual functions. It can be used as an external 14.318-MHz crystal
connection or as an external reference frequency input.
Crystal Connection
.
Connection for an external 14.318-MHz crystal
output.
CPU Clock Output.
Differential CPU clock outputs.
CPU Clock Output
.
Differential CPU clock outputs.
Do Not Connect.
66-MHz Clock Output.
3.3V 66-MHz clock from internal VCO.
48- or 66-MHz Clock Output
. 3.3V selectable through external SELVCH
strapping resistor and SMBus to be 66-MHz or 48-MHz. Default is 66-MHz.
0 = 66 MHz, 1 = 48 MHz
66-MHz Clock Output
. 3.3V 66-MHz clock from internal VCO. Reset or
Power-down Mode Select. Selects between RESET# output or PWRDWN#
input for the PWRDWN#/RESET# pin. Default is RESET#. 0 = PD#, 1 =
RESET
Free Running PCI Output
.
33-MHz clocks divided down from 3V66.
PCI Clock Output
.
33-MHz clocks divided down from 3V66.
5
XOUT
O, SE
39, 42, 45
38, 41, 44
36, 35
30, 29
25
CPUT(0:1,ITP)
CPUC(0:1,ITP)
DNC
3V66(0:1)
3V66_3/VCH/SELVCH
O, DIF
O, DIF
O, SE
I/O, SE
PD
26
3V66_2/MODE
I/O, SE
PU
7, 8, 9
12, 13, 14,
15, 18, 19
22
21
46
PCIF(0:2)
PCI(0:5)
O, SE
O, SE
USB_48
DOT_48
IREF
O, SE
O, SE
I
Fixed 48-MHz clock output
.
Fixed 48-MHz clock output
.
Current Reference
. A precision resistor is attached to this pin which is
connected to the internal current reference.
3.3V LVTTL input for Power-down# active LOW
. Watchdog Timeout
Reset Output
3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E]
input (active LOW)
.
SMBus compatible SDATA
.
SMBus compatible SCLOCK
.
3.3V Power supply for PLL
.
Ground for PLL
.
3.3V Power supply for outputs
.
20
RESET#/PD#
I/O, PU
33
VTT_PWRGD#
I
32
31
48
47
3, 10, 16,
24, 27, 34,
40
6, 11, 17,
23, 28, 37,
43
SDATA
SCLK
VDDA
VSSA
VDD(REF,PCI,48,3V66,C
PU,ITP)
I/O
I
PWR
GND
PWR
VSS(REF,PCI,48,3V66,
CPU,ITP)
GND
Ground for outputs
.
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| CY28408ZC | 制造商:Cypress Semiconductor 功能描述: |
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