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參數(shù)資料
| 型號： | CY28401OCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100-MHz Differential Buffer for PCI Express and SATA |
| 中文描述： | 28401 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 235K |
| 代理商： | CY28401OCT |
CY28401
Document #: 38-07592 Rev. **
Page 7 of 14
SRC_STOP# Clarification
The SRC_STOP# signal is an active low input used for clean
stopping and starting the DIFT/C outputs (valid clock must be
present on SRCT/C_IN). The SRC_STOP# signal is a
debounced signal in that it’s state must remain unchanged
during two consecutive rising edges of DIFC to be recognized
as a valid assertion or deassertion. (The assertion and
deassertion of this signal is absolutely asynchronous).
SRC_STOP# Assertion
The impact of asserting the SRC_STOP# pin is all DIF outputs
that are set in the control registers to stoppable via assertion
of SRC_STOP# are stopped after their next transition. When
the control register SRC_STOP# three-state bit is
programmed to ‘0’, the final state of all stopped DIFT/C signals
is DIFT clock = High and DIFC = Low. There will be no change
to the output drive current values, DIFT will be driven high with
a current value equal 6 x Iref, and DIFC will not be driven.
When the control register SRC_STOP# three-state bit is
programmed to ‘1’, the final state of all stopped DIF signals is
low, both DIFT clock and DIFC clock outputs will not be driven.
SRC_STOP# Deassertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2-6 DIFT/C clock
periods (2 clocks are shown) with all DIFT/C outputs resuming
simultaneously. If the control register three-state bit is
programmed to ‘1’ (three-state), then all stopped DIFT outputs
will be driven high within 10 ns of SRC_STOP# deassertion to
a voltage greater than 200 mV.
S2
Wait for Input
Clock &
PWRDWN# De-
assertion
PWRDWN# Asserted
S1
Delay
>0.25ms
S0
Power Off
S3
Normal
Operation
No Input Clock
Figure 3. Buffer Power-up State Diagram
Table 5. SRC_STOP# Functionality
[6]
SRC_STOP#
1
0
DIFT
Normal
DIFC
Normal
Low
Iref * 6 or Float
DIFC (Stoppable)
DIFT (Stoppable)
DIFC(Free Running
DIFT(Free Running
PWRDWN#
1mS
SRC_STOP#
Figure 4. SRC_STOP# = Driven, PWRDWN# = Driven
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| CY28405OXCT | CK409-Compliant Clock Synthesizer |
| CY28405OC | CK409-Compliant Clock Synthesizer |
| CY28405OCT | Circular Connector; No. of Contacts:6; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-6 |
| CY28405OXC | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Crimp; Body Material:Aluminum; Series:PT06; No. of Contacts:3; Connector Shell Size:8; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28401OXC | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCIe & SATA 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28401OXCT | 功能描述:時鐘緩沖器 100 MHz Diff Buffer PCIe & SATA 1in 4out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28404 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:CK409-Compliant Clock Synthesizer |
| CY28404OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CK409-COMPLIANT CLOCK SYNTHESIZER |
| CY28404OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CK409-COMPLIANT CLOCK SYNTHESIZER |
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