參數資料
型號： CY28349BOCT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： FTG for Intel Pentium 4 CPU and Chipsets
中文描述： 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁數： 5/22頁
文件大?。?/td> 174K
代理商： CY28349BOCT
CY28349B
Document #: 38-07454 Rev. *A
Page 5 of 22
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or
disabled.
The register associated with the Serial Data Interface
initializes to its default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts Byte Write, byte read,
Block Write and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code, as
described in
Table 1
.
The Block Write and Block Read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol.
The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations,
these bits should be
‘
0000000
’
.
6:0
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
Start
2:8
Slave address
–
7 bits
9
Write
10
Acknowledge from slave
Command Code
–
8 bits
‘
00000000
’
stands for block operation
19
Acknowledge from slave
20:27
Byte Count
–
8 bits
28
Acknowledge from slave
29:36
Data byte 0
–
8 bits
37
Acknowledge from slave
38:45
Data byte 1
–
8 bits
46
Acknowledge from slave
...
Data Byte N/Slave Acknowledge...
...
Data Byte N
–
8 bits
...
Acknowledge from slave
...
Stop
Block Read Protocol
Description
Bit
1
2:8
9
10
Description
Start
Slave address
–
7 bits
Write
Acknowledge from slave
Command Code
–
8 bits
‘
00000000
’
stands for block operation
Acknowledge from slave
Repeat start
Slave address
–
7 bits
Read
Acknowledge from slave
Byte count from slave
–
8 bits
Acknowledge
Data byte from slave
–
8 bits
Acknowledge
Data byte from slave
–
8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave
–
8 bits
Not Acknowledge
Stop
11:18
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
...
...
...
...
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
Start
2:8
Slave address
–
7 bits
Byte Read Protocol
Description
Bit
1
2:8
Description
Start
Slave address
–
7 bits
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相關代理商/技術參數
參數描述
CY28349BOXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349BOXCT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349OC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY28349OCT 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
CY28349OXC 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets
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