參數(shù)資料
型號(hào)： CY28341OC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
中文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： SSOP-56
文件頁(yè)數(shù)： 12/21頁(yè)
文件大?。?/td> 189K
代理商： CY28341OC
CY28341
Document #: 38-07367 Rev. *A
Page 12 of 21
Tr / Tf
TCCJ
24MHz
TDC
TPeriod
Tr / Tf
TCCJ
REF
TDC
TPeriod
Tr / Tf
TCCJ
DDR
VX
48MHz Rise and Fall Times
48MHz Cycle to Cycle Jitter
1.0
4.0
500
1.0
4.0
500
1.0
4.0
500
ns
ps
11,13
11,14,15
24MHz Duty Cycle
24MHz Period
24MHz Rise and Fall Times
24MHz Cycle to Cycle Jitter
45
55
45
55
45
55
%
ns
ns
ps
7,11,14
7,11,14
11,13
11,14,15
41.660
1.0
41.667
4.0
500
41.660
1.0
41.667
4.0
500
41.660
1.0
41.667
4.0
500
REF Duty Cycle
REF Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
45
55
71.0
4.0
1000
45
55
71.0
4.0
1000
45
55
71.0
4.0
1000
%
ns
ns
ps
7,11,14
7,11,14
11,13
11,14,15
69.8413
1.0
69.8413
1.0
69.8413
1.0
Crossing Point Voltage of
DDRT/C
Differential Voltage Swing
0.5*V
DD
–
0.2
0.7
0.5*V
DDD
+
0.2
V
DDD
+ 0.6
0.5*V
DDD
–
0.2
0.7
0.5*V
DDD
+ 0.2
V
DDD
+
0.6
55
15.3
3
100
0.5*V
DDD
–
0.2
0.7
0.5*V
DDD
+0.2
V
DDD
+
0.6
55
10.2
3
100
V
19
VD
V
20
TDC
TPeriod
Tr / Tf
TSKEW
DDRT/C(0:5) Duty Cycle
DDRT/C(0:5) Period
DDRT/C(0:5) Rise/Fall Slew Rate
DDRT/C to Any DDRT/C Clock
Skew
DDRT/C(0:5) Cycle to Cycle Jitter
DDRT/C(0:5) Half-period Jitter
BUF_IN to Any DDRT/C Delay
FBOUT to Any DDRT/CSkew
All Clock Stabilization from
Power-up
45
9.85
1
55
10.2
3
100
45
45
9.85
1
%
ns
V/ns
ps
21
21
13
14.85
1
11,15,21
TCCJ
THPJ
TDelay
TSKEW
tstable
±75
±100
4
100
3
±75
±100
4
100
3
±75
±100
4
100
3
ps
ps
ns
ps
ms
11,15,21
11,15,21
11,14
11,14
18
1
1
1
Notes:
5.
6.
7.
8.
All outputs loaded as per maximum capacitive load table.
All outputs are not loaded.
This parameter is measured as an average over a 1-
μ
s duration, with a crystal center frequency of 14.31818 MHz.
This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
When crystal meets minimum 40-ohm device series resistance specification.
10. Measured between 0.2V
and 0.7V
.
11.
All outputs loaded as per loading specified in the Table 11.
12. When X
is driven from an external clock source (3.3V parameters apply).
13. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
between 20% and 80% for differential signals.
14. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.
15. This measurement is applicable with Spread ON or spread OFF.
16. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals)
17. Probes are placed on the pins, and measurements are acquired at 0.4V.
18. The time specified is measured from when all VDD
’
s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within
the specifications.
19. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
20. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary
DDRC (and CPUCS_C) one.
21. Measured at VX, or where subtraction of CLK-CLK# crosses 0 volts.
22. See Figure 10. for 0.7V loading specification.
23. Measured from Vol=0.175V to Voh=0.525V.
24. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as
“
the instantaneous
difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time
”
. This parameter is
designed for waveform symmetry.
25. Measurement taken from differential waveform, from -0.35V to +0.35V.
26. Measured in absolute voltage, i.e. single-ended measurement.
27. Measured at VX between the rising edge and the following falling edge of the signal.
28. Measured at VX between the falling edge and the following rising edge of the signal.
29. This parameter is intended to be 0.45*Tperiod(min) for minimum spec. and 0.55*Tperiod(min) for maximum spec.
30. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).
9.
AC Parameters
(continued)
Parameter
Description
100 MHz
Min.
133MHz
Min.
200 MHz
Min.
Unit
Notes
[4]
Max.
Max
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY28341OC-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY28341OC-2T 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems
CY28341OC-3 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems
CY28341OC-3T 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
CY28341OCT 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems
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