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參數(shù)資料
| 型號： | CY28339ZCXT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Intel CK408 Mobile Clock Synthesizer |
| 中文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.240 INCH, LEAD FREE, TSSOP2-48 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 224K |
| 代理商： | CY28339ZCXT |
CY28339
Document #: 38-07507 Rev. *A
Page 11 of 18
Table 4. CPU Clock Current Select Function
USB_48M and DOT_48M Phase Relationship
The USB_48M and DOT_48M clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See
Figure 11
.
66IN to 66BUFF(0:2) Buffered Prop Delay
The 66IN to 66BUFF(0:2) output delay is shown in
Figure 12
.The Tpd is the prop delay from the input pin (66IN)
to the output pins (66BUFF[0:2]). The outputs’ variation of Tpd
is described in the AC parameters section of this data sheet.
The measurement taken at 1.5V.
66BUFF(0:2) to PCI Buffered Clock Skew
Figure 13
shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
Figure 1
shows the timing relationship between 3V66_0 and
PCI(0:2,4:8) and PCIF when configured to run in the unbuf-
fered mode.
Board Target Trace/Term Z
50
50
Reference R, Iref – Vdd (3*Rr)
Rr = 330 1%, Iref = 3.33mA
Rr = 475 1%, Iref = 2.32mA
Output Current
Ioh = 6*Iref
Ioh = 6*Iref
Voh @ Z
1.0V @ 50
0.7V @ 50
Table 5. Group Timing Relationship and Tolerances
Description
Offset
2.5 ns
0.0 ns
2.5 ns
Tolerance
±
1.0 ns
±
1.0 ns
±
1.0 ns
Conditions
3V66 to PCI
USB_48M to DOT_48M Skew
66BUFF(0:2) to PCI offset
3V66 leads PCI (unbuffered mode)
0 degrees phase shift
66BUFF leads PCI (buffered mode)
USB_48M
DOT_48M
Figure 11. USB_48M and DOT_48M Phase Relationship
66IN
66B
Tpd
Figure 12. 66IN to 66BUFF(0:2) Output Delay Figure
66B
PCI
PCIF
1.5-
3.5ns
Figure 13. Buffer Mode – 33V66_0; 66BUFF(0:2) Phase Relationship
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| CY28339ZXC | 功能描述:IC CLOCK SYNTHESIZER 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| CY28339ZXCT | 功能描述:IC CLOCK SYNTHESIZER 48-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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| CY28341-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems |
| CY28341-2_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
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