參數(shù)資料
型號: CY28329OXCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: DC Fan; Series:Muffin XL; Depth:38mm; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No
中文描述: 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: LEAD FREE, SSOP-56
文件頁數(shù): 2/17頁
文件大?。?/td> 290K
代理商: CY28329OXCT
CY28329
Document #: 38-07040 Rev. *E
Page 2 of 17
Pin Description
Name
Pins
Description
REF
XTAL_IN
XTAL_OUT
CPU, CPU [0:3]#
56
2
3
44, 45, 48, 49,
51, 52, 53, 54
33
35
24
21, 22, 23
3.3V 14.318-MHz clock output
14.318-MHz crystal input
14.318-MHz crystal input
Differential CPU clock outputs
3V66_0
3V66_1/VCH
66IN/3V66_5
66BUFF [0:2]
/3V66 [2:4]
PCI_F [0:2]
PCI [0:6]
3.3V 66-MHz clock output
3.3V selectable through SMBus to be 66 MHz or 48 MHz
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO
66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO
5, 6, 7,
10, 11, 12, 13, 16,
17, 18
39
38
40
55
42
33-MHz clocks divided down from 66Input or divided down from 3V66
PCI clock outputs divided down from 66Input or divided down from 3V66
USB
DOT
S2
S1
IREF
Fixed 48-MHz clock output
Fixed 48-MHz clock output
Special 3.3V 3-level input for Mode selection
3.3V LVTTL inputs for CPU frequency selection
A precision resistor is attached to this pin which is connected to the internal current
reference
3.3V LVTTL input for selecting the current multiplier for the CPU outputs
3.3V LVTTL input for Power_Down# (active LOW)
.
Do not add any decoupling capac-
itors. Use an external 1.0-K
pull-up resistor.
3.3V LVTTL input for PCI_STOP# (active LOW)
3.3V LVTTL input is a level-sensitive strobe used to determine when S[1:2] and
MULT0 inputs are valid and OK to be sampled (Active LOW)
. Once VTTPWRGD# is
sampled LOW, the status of this output will be ignored.
SMBus-compatible SDATA
SMBus-compatible Sclk
3.3V power supply for outputs
MULT0
PD#
43
25
PCI_STOP#
VTTPWRGD#
34
28
SDATA
SCLK
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48 MHz,
VDD_CPU
VDD_CORE
GND_REF,
GND_PCI,
GND_3V66,
GND_IREF,
VDD_CPU
GND_CORE
29
30
1, 8, 14, 19, 32,
37, 46, 50
26
4, 9, 15, 20, 31,
36, 41, 47
3.3V power supply for PLL
Ground for outputs
27
Ground for PLL
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