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參數(shù)資料
| 型號： | CY28323OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BROOKDALE GPENT4 48SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 248MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
CY28323PVC
... Document #: 38-07004 Rev. *B Page Page 9 of 21 of 21
Data Byte 8
Bit
Pin#
Name
Pin Description
Power On
Default
Bit 7
--
Reserved
0
Bit 6
--
Reserved
0
Bit 5
--
WD_TIMER4
These bits store the time-out value of the WATCHDOG
timer. The scale of the timer is determine by the prescaler.
The timer can support a value of 150 ms to 4.8 sec when
the prescaler is set to 150 ms. If the prescaler is set to
2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog Timer reaches “0,” it will set the
WD_TO_STATUS bit and generate Reset if RST_EN_WD
is enabled.
1
Bit 4
--
WD_TIMER3
1
Bit 3
--
WD_TIMER2
1
Bit 2
--
WD_TIMER1
1
Bit 1
--
WD_TIMER0
1
Bit 0
--
WD_PRE_SCALER
0 = 150 ms
1 = 2.5 sec
0
Data Byte 9
Bit
Pin#
Name
Pin Description
Power On
Default
Bit 7
--
48MHz_DRV
48-MHz & 24_48-MHz clock output drive strength
0 = Normal
1 = High Drive
(Recommend to set to high drive if this output is being used
to drive both USB and SIO devices in Intel Brookdale - G
platforms)
0
Bit 6
--
PCI_DRV
PCI clock output drive strength
0 = Normal
1 = High Drive
0
Bit 5
--
3V66_DRV
3V66 clock output drive strength
0 = Normal
1 = High Drive
0
Bit 4
--
RST_EN_WD
This bit will enable the generation of a Reset pulse when a
Watchdog Timer time-out occurs.
0 = Disabled
1 = Enabled
0
Bit 3
--
RST_EN_FC
This bit will enable the generation of a Reset pulse after a
frequency change occurs.
0 = Disabled
1 = Enabled
0
Bit 2
--
WD_TO_STATUS
Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = time-out occurred (Read); Clear WD_TO_STATUS
(Write)
0
Bit 1
--
WD_EN
0 = Stop and reload Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after
a frequency change occurs.
Note: CY28323 will generate system reset, reload a
recovery frequency, and lock itself into a recovery
frequency mode after a Watchdog timer time-out occurs.
Under recovery frequency mode, CY28323 will not respond
to any attempt to change output frequency via the SMBus
control bytes. System software can unlock CY28323 from
its recovery frequency mode by clearing the WD_EN bit.
0
Bit 0
--
Reserved
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28323PVC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28324 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel Pentium 4 CPU and Chipsets |
| CY28324_02 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets |
| CY28324PVC | 制造商:Cypress Semiconductor 功能描述:PLL Frequency Generator Dual 48-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28324PVCT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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