參數(shù)資料
型號(hào)： CY24207ZC-1
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： MediaClock PDP Clock Generator
中文描述： 67.425 MHz, VIDEO CLOCK GENERATOR, PDSO16
封裝： 4.40 MM, TSSOP-16
文件頁(yè)數(shù)： 3/6頁(yè)
文件大?。?/td> 46K
代理商： CY24207ZC-1
CY24207
Document #: 38-07553 Rev. *A
Page 3 of 6
Absolute Maximum Conditions
Supply Voltage (V
DD
, AV
DDL
, V
DDL
)..................–0.5 to +7.0V
DC Input Voltage........................................–0.5V to V
DD
+0.5
Storage Temperature (Non-condensing).....–55
°
C to +125
°
C
Junction Temperature ................................ –40
°
C to +125
°
C
Pullable Crystal Specifications
Data Retention @ Tj = 125
°
C................................> 10 years
Package Power Dissipation......................................350 mW
ESD (Human Body Model) MIL-STD-883....................2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Parameter
F
NOM
Description
Conditions
Min.
Typ.
27.0
Max. Units
Nominal crystal frequency
Parallel resonance, fundamental mode, AT
cut
MHz
C
LNOM
R
1
R
3
/R
1
Nominal load capacitance
Equivalent series resistance (ESR)
Ratio of third overtone mode ESR to
fundamental mode ESR
Crystal drive level
Third overtone separation from 3*F
NOM
High side
Third overtone separation from 3*F
NOM
Low side
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
14
pF
Fundamental mode
Ratio used because typical R
1
values are
much less than the maximum spec
No external series resistor assumed
25
3
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
0.5
2
mW
ppm
ppm
pF
300
–150
7
250
21.6
180
14.4
18
fF
Recommended Operating Conditions
Parameter
V
DD
/AV
DDL
/V
DDL
T
A
C
LOAD
t
PU
Description
Min.
3.135
0
Typ.
3.3
Max.
3.465
70
15
500
Unit
V
°C
pF
ms
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power-up time for all V
DD
s to reach minimum specified
voltage (power ramps must be monotonic)
0.05
DC Electrical Specifications
Parameter
2
I
OH
Output High Current
I
OL
Output Low Current
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
VDD
Supply Current
I
VDDL
Supply Current
C
IN
Input Capacitance
f
XO
V
CXO
pullability range
V
VCXO
V
CXO
input range
R
UP
Pull-up resistor on inputs V
DD
= 3.14 to 3.47V, measured at V
IN
= 0V
Name
Description
Min.
12
12
0.7
Typ.
24
24
Max.
Unit
mA
mA
V
DD
V
DD
mA
mA
pF
ppm
V
k
V
OH
= V
DD
– 0.5, V
DD
/V
DDL
= 3.3V
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
AV
DD
/V
DD
Current
V
DDL
Current (V
DDL
= 3.47V)
excluding XIN and XOUT
0.3
25
20
7
±200
0
V
DD
150
100
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