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參數(shù)資料
| 型號： | CY241V8A-02 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MPEG Clock Generator with VCXO(帶VCXO的MPEG時鐘發(fā)生器) |
| 中文描述： | 的MPEG時鐘發(fā)生器，石英振蕩器（帶石英振蕩器的時鐘發(fā)生器的MPEG） |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 128K |
| 代理商： | CY241V8A-02 |
PRELIMINARY
CY241V08A-02
Document #: 38-07674 Rev. *A
Page 3 of 6
Absolute Maximum Conditions
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage......................................–0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing).....–55
°
C to +125
°
C
Junction Temperature ................................ –40
°
C to +125
°
C
Pullable Crystal Specifications
[1]
Data Retention @ Tj = 125
°
C................................> 10 years
Package Power Dissipation......................................350 mW
ESD (Human Body Model) MIL-STD-883.................> 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Parameter
F
NOM
Description
Comments
Min.
–
Typ.
27
Max.
–
Unit
MHz
Nominal crystal frequency
Parallel resonance, fundamental mode, AT
cut
C
LNOM
R
1
R
3
/R
1
Nominal load capacitance
Equivalent series resistance (ESR)
Ratio of third overtone mode ESR to
fundamental mode ESR
Crystal drive level
Third overtone separation from 3*F
NOM
Third overtone separation from 3*F
NOM
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
Recommended Operating Conditions
–
–
3
14
–
–
–
25
–
pF
–
Fundamental mode
Ratio used because typical R
1
values are
much less than the maximum spec
No external series resistor assumed
High side
Low side
DL
F
3SEPHI
F
3SEPLO
C
0
C
0
/C
1
C
1
150
300
–
–
180
14.4
–
–
–
–
–
18
–
–
μ
W
ppm
ppm
pF
–
fF
–150
7
250
21.6
Parameter
Description
Min.
3.135
0
–
0.05
Typ.
3.3
–
–
–
Max.
3.465
70
15
500
Unit
V
°C
pF
ms
V
DD
T
A
C
LOAD
t
PU
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power-up time for all V
DD
pins to reach minimum specified
voltage (power ramps must be monotonic)
DC Electrical Specifications
Parameter
I
OH
I
OL
C
IN
V
VCXO
f
XO[2]
Name
Description
Min.
12
12
–
0
–
115
–
Typ.
24
24
–
–
–
–
–
Max.
–
–
7
V
DD
–115
–
35
Unit
mA
mA
pF
V
ppm
ppm
mA
Output HIGH Current
Output LOW Current
Input Capacitance
VCXO Input Range
VCXO Pullability Range
V
OH
= V
DD
– 0.5V, V
DD
= 3.3V
V
OL
= 0.5V, V
DD
= 3.3V
Except XIN, XOUT pins
Low Side
High Side
I
VDD
Supply Current
AC Electrical Specifications
(V
DD
= 3.3V)
[3]
Parameter
[3]
DC
Output Duty Cycle
ER
Rising Edge Rate
Name
Description
Min.
45
0.8
Typ.
50
1.4
Max.
55
–
Unit
%
V/ns
Duty Cycle is defined in
Figure 1
, 50% of V
DD
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, C
LOAD
= 15 pF. See
Figure 2
.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, C
LOAD
= 15 pF. See
Figure 2
.
27-MHz Clock Jitter
EF
Falling Edge Rate
0.8
1.4
–
V/ns
t
9
Notes:
1.
2.
Peak-to-peak Period Jitter
–
–
100
ps
Crystals that meet this specification includes: Ecliptek ECX-5808-27.000M
–115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less
board capacitance.
Not 100% tested.
3.
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| CY241V8ASXC-01 | 功能描述:鎖相環(huán) - PLL MPEG Clk Genratr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY241V8ASXC-01T | 功能描述:鎖相環(huán) - PLL MPEG Clk Genratr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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